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CS4207
Low-power, 4-in / 6-out HD Audio CODEC with Headphone Amp
DIGITAL to ANALOG FEATURES
DAC1 (Headphone)
ANALOG to DIGITAL FEATURES
ADC1 & ADC2
- - - - - - - -
101 dB Dynamic Range (A-wtd) -89 dB THD+N Integrated Negative-voltage Regulator No DC-blocking Capacitor Required 50 mW Power/Channel into 16 110 dB Dynamic Range (A-wtd) -94 dB THD+N Differential Balanced or Single-ended
Headphone Amplifier - GND Centered
- - - -
DAC2 & DAC3 (Line Outs)
105 dB Dynamic Range (A-wtd) -88 dB THD+N Differential Balanced or Single-ended Inputs Analog Programmable Gain Amplifier (PGA) 12 dB, 1.0 dB Steps, with Zero Cross Transitions and Mute Pre-amplifier with Selectable 0 dB, +10 dB, +20 dB, and +30 dB Gain Settings Programmable, Low-noise MIC Bias Level
MIC Inputs
- -
Each DAC Supports 32 kHz to 192 kHz Sample
Rates Independently.
Digital Volume Control
Each ADC Supports 8 kHz to 96 kHz Sample
Rates Independently
Additional Digital Attenuation Control
- -
+6.0 dB to -57.5 dB in 0.5 dB Steps Zero Cross and/or Soft Ramp Transitions
Independent Support of D0 and D3 Power
States for Each DAC
Fast D3 to D0 Transition
- -
-13.0 dB to -51.0 dB in 1.0 dB steps Zero Cross and/or Soft Ramp Transitions
Digital Interface for Two Dual Digital Mic Inputs Independent Support of D0 and D3 Power
-
Audio Playback in Less Than 50 ms
States for Each ADC
VD (1.5 V to 1.8 V) VA, VA_REF (3.3 V to 5.0 V) VA_HP (3.3 V to 5.0 V)
Chrg Pump Buck +VHP Chrg Pump Invert -VHP
Level Translator
Vol/Mute HD Audio Interface
SRC & Multibit Modulator SRC & Multibit Modulator SRC & Multibit Modulator Digital Filter & SRC Digital Filter & SRC
2-Chnl DAC1 2-Chnl DAC2 2-Chnl DAC3
Headphone Amp - GND Centered Line Out Line Out
Left HP Out Right HP Out +Left Line Out + Right Line Out +Left Line Out + Right Line Out -
HD Audio Bus VL_HD (1.5 V to 3.3 V) GPIO S/PDIF OUT 2 S/PDIF OUT 1 VL_IF (3.3 V) S/PDIF IN D-Mic Clock D-Mic In
Vol/Mute
GPIO SPDIF TX2 SPDIF TX1
HD Bus Fs
Vol/Mute
Level Translator
Vol/Boost/ Mute
2-Chnl ADC1
PGA
+ - Line/Mic In L Line/Mic In R + + - Mic/Line In L +Mic/Line In R Mic Bias SENSE_A
128Fs Clock Multiplier SPDIF RX SRC
Vol/Boost/ Mute
2-Chnl ADC2
PGA
MIC Bias
SPDIF RX
Jack Sense
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2009 (All Rights Reserved)
APR '09 DS880F1
CS4207
Digital Audio Interface Receiver
Complete EIAJ CP1201, IEC-60958, S/PDIF
General Description
The CS4207 is a highly integrated multi-channel lowpower HD Audio CODEC featuring 192 kHz DACs, 96 kHz ADCs, 192 kHz S/PDIF Transmitters and Receiver, Microphone pre-amp and bias voltage, and a ground centered Headphone driver. Based on multi-bit, delta-sigma modulation, it allows infinite sample rate adjustment between 32 kHz and 192 kHz. The ADC input path allows control of a number of features. The microphone input path includes a selectable programmable-gain pre-amplifier stage and a low-noise MIC bias voltage supply. A PGA is available for line and microphone inputs and provides analog gain with soft ramp and zero cross transitions. The ADC also features an additional digital volume attenuator with soft ramp transitions. The stereo headphone amplifier is powered from a separate internally generated positive supply, with an integrated charge pump providing a negative supply. This allows a ground-centered analog output with a wide signal swing and eliminates external DC-blocking capacitors. The integrated digital audio interface receiver and transmitters utilize a 24-bit, high-performance, monolithic CMOS stereo asynchronous sample rate converter to clock align the PCM samples to/from the S/PDIF interfaces. Auto detection of non-PCM encoded data disables the sample rate conversion to preserve bit accuracy of the data. In addition to its many features, the CS4207 operates from a low-voltage analog and digital core, making this part ideal for portable systems that require low power consumption in a minimal amount of space. The CS4207 is available in a 48-pin WQFN package in both Automotive (-40C to +105C) and Commercial (40C to +85C) grades. The CS4207 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please refer to "Ordering Information" on p 142 for complete ordering information.
Compatible Receiver
32 kHz to 192 kHz Sample Rate Range Automatic Detection of Compressed Audio
Streams
Integrated Sample Rate Converter
- - - -
128 dB Dynamic Range -120 dB THD+N Supports Sample Rates up to 192 kHz 1:1 Input/Output Sample Rate Ratios
Digital Audio Interface Transmitters
Two Independent EIAJ CP1201, IEC-60958,
S/PDIF Compatible Transmitters
32 kHz to 192 kHz Sample Rate Range
System Features
Very Low D3 Power Dissipation of <7 mW
- -
Jack Detect Active in D3 HDA Bus BITCLK not required for D3 State
Jack Detect Does not Require HDA Bus
BITCLK
All Configuration Settings are Preserved in D3
State
Pop/Click Suppression in State Transitions Detects Wake Event and Generates Power
State Change Request when HDA Bus Controller is in D3 Variable Power Supplies - 1.5 V to 1.8 V Digital Core Voltage - 3.3 V to 5.0 V Analog Core Voltage - 3.3 V to 5.0 V Headphone Drivers - 1.5 V to 3.3 V HD Bus Interface Logic - 3.3 V Interface Logic levels for GPIO, S/PDIF, and Digital Mic.
Individual Power-down Managed
-
ADCs, DACs, PGAs, Headphone Driver, S/PDIF Receiver, and Transmitters
2
DS880F1
CS4207
TABLE OF CONTENTS
1. PIN DESCRIPTIONS .............................................................................................................................. 8 1.1 CS4207 Pinout: ................................................................................................................................ 8 1.2 Digital I/O Pin Characteristics ........................................................................................................ 10 2. TYPICAL CONNECTION DIAGRAMS ................................................................................................. 11 3. CHARACTERISTIC AND SPECIFICATIONS ...................................................................................... 13 RECOMMENDED OPERATING CONDITIONS .................................................................................. 13 ABSOLUTE MAXIMUM RATINGS ...................................................................................................... 13 ANALOG INPUT CHARACTERISTICS (COMMERCIAL - CNZ) ......................................................... 14 ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) ......................................................... 15 ADC DIGITAL FILTER CHARACTERISTICS ...................................................................................... 16 DIGITAL MICROPHONE CHARACTERISTICS .................................................................................. 16 ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ) ..................................................... 17 ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) ..................................................... 19 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ............................. 21 DC ELECTRICAL CHARACTERISTICS .............................................................................................. 21 DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS .................................................... 22 HD AUDIO BUS SPECIFICATIONS & CHARACTERISTICS .............................................................. 22 S/PDIF TRANSMITTER/RECEIVER SPECIFICATIONS & CHARACTERISTICS .............................. 22 POWER CONSUMPTION ................................................................................................................... 23 4. CODEC RESET AND INITIALIZATION ............................................................................................... 24 4.1 Link Reset ...................................................................................................................................... 24 4.2 Function Group Reset .................................................................................................................... 24 4.3 Codec Initialization ......................................................................................................................... 24 4.4 D3 Lower Power State Support ..................................................................................................... 25 4.5 Extended Power States Supported (EPSS) ................................................................................... 25 4.6 Power State Settings Reset (PS-SettingsReset) ........................................................................... 27 4.7 Register Settings Across Resets ................................................................................................... 28 5. PRESENCE DETECTION ..................................................................................................................... 30 5.1 Jack Detection Circuit .................................................................................................................... 30 5.1.1 Presence Detection and Unsolicited Response .................................................................... 30 5.1.2 S/PDIF Receiver Presence Detect ........................................................................................ 31 6. HD AUDIO CODEC SUPPORTED VERBS AND RESPONSES ......................................................... 32 6.1 Software Programming Model ....................................................................................................... 32 6.1.1 Node ID Summary ................................................................................................................. 33 6.1.2 Pin Configuration Register Defaults ...................................................................................... 34 6.2 Root Node ...................................................................................................................................... 35 6.2.1 Vendor and Device ID ........................................................................................................... 35 6.2.2 Revision ID ............................................................................................................................ 35 6.2.3 Subordinate Node Count ....................................................................................................... 35 6.3 Audio Function Group (Node ID = 01h) ......................................................................................... 36 6.3.1 Subordinate Node Count ....................................................................................................... 36 6.3.2 Function Group Type ............................................................................................................. 36 6.3.3 Audio Function Group Capabilities ........................................................................................ 36 6.3.4 Supported PCM Size, Rates ................................................................................................. 37 6.3.5 Supported Stream Formats ................................................................................................... 38 6.3.6 Supported Power States ....................................................................................................... 38 6.3.7 GPIO Capabilities .................................................................................................................. 39 6.3.8 Power States ......................................................................................................................... 40 6.3.9 GPIO Data ............................................................................................................................. 41 6.3.10 GPIO Enable Mask .............................................................................................................. 42 6.3.11 GPIO Direction .................................................................................................................... 42 6.3.12 GPIO Sticky Mask ............................................................................................................... 42 DS880F1 3
CS4207
6.3.13 Subsystem ID ...................................................................................................................... 43 6.3.14 Function Reset .................................................................................................................... 43 6.4 DAC1, DAC2, DAC3 Output Converter Widgets (Node ID = 02h, 03h, 04h) ................................. 44 6.4.1 Audio Widget Capabilities ..................................................................................................... 44 6.4.2 Supported PCM Size, Rates ................................................................................................. 45 6.4.3 Supported Stream Formats ................................................................................................... 45 6.4.4 Supported Power States ....................................................................................................... 46 6.4.5 Output Amplifier Capabilities ................................................................................................. 46 6.4.6 Power States ......................................................................................................................... 47 6.4.7 Converter Stream, Channel ................................................................................................... 48 6.4.8 Converter Format .................................................................................................................. 48 6.4.9 Amplifier Gain/Mute ............................................................................................................... 50 6.5 ADC1, ADC2 Input Converter Widgets (Node ID = 05h, 06h) ....................................................... 52 6.5.1 Audio Widget Capabilities ..................................................................................................... 52 6.5.2 Supported PCM Size, Rates ................................................................................................. 53 6.5.3 Supported Stream Formats ................................................................................................... 53 6.5.4 Input Amplifier Capabilities .................................................................................................... 54 6.5.5 Connection List Length .......................................................................................................... 54 6.5.6 Supported Power States ....................................................................................................... 55 6.5.7 ADC1 Connection List Entry .................................................................................................. 55 6.5.8 ADC1 Connection Select Control .......................................................................................... 55 6.5.9 ADC2 Connection List Entry .................................................................................................. 56 6.5.10 ADC2 Connection Select Control ........................................................................................ 56 6.5.11 Power States ....................................................................................................................... 57 6.5.12 Converter Stream, Channel ................................................................................................. 58 6.5.13 Converter Format ................................................................................................................ 58 6.5.14 Amplifier Gain/Mute ............................................................................................................. 60 6.6 S/PDIF Receiver Input Converter Widget (Node ID = 07h) ........................................................... 62 6.6.1 Audio Widget Capabilities ..................................................................................................... 62 6.6.2 Supported PCM Size, Rates ................................................................................................. 63 6.6.3 Supported Stream Formats ................................................................................................... 63 6.6.4 Connection List Length .......................................................................................................... 64 6.6.5 Supported Power States ....................................................................................................... 64 6.6.6 Connection List Entry ............................................................................................................ 64 6.6.7 Power States ......................................................................................................................... 65 6.6.8 Converter Stream, Channel ................................................................................................... 66 6.6.9 Converter Format .................................................................................................................. 66 6.6.10 Digital Converter Control ..................................................................................................... 68 6.7 S/PDIF Transmitter 1, S/PDIF Transmitter 2 Output Converter Widgets (Node ID = 08h, 14h) .... 69 6.7.1 Audio Widget Capabilities ..................................................................................................... 69 6.7.2 Supported PCM Size, Rates ................................................................................................. 70 6.7.3 Supported Stream Formats ................................................................................................... 70 6.7.4 Supported Power States ....................................................................................................... 71 6.7.5 Power States ......................................................................................................................... 71 6.7.6 Converter Stream, Channel ................................................................................................... 72 6.7.7 Converter Format .................................................................................................................. 73 6.7.8 Digital Converter Control ....................................................................................................... 75 6.8 Headphone Pin Widget (Node ID = 09h) ....................................................................................... 77 6.8.1 Audio Widget Capabilities ..................................................................................................... 77 6.8.2 Pin Capabilities ...................................................................................................................... 77 6.8.3 Connection List Length .......................................................................................................... 78 6.8.4 Supported Power States ....................................................................................................... 78 6.8.5 Connection List Entry ............................................................................................................ 79 6.8.6 Power States ......................................................................................................................... 79 4 DS880F1
CS4207
6.8.7 Pin Widget Control ................................................................................................................ 80 6.8.8 Unsolicited Response Control ............................................................................................... 81 6.8.9 Pin Sense .............................................................................................................................. 81 6.8.10 Configuration Default ........................................................................................................... 83 6.9 Line Out 1 Pin Widget (Node ID = 0Ah) ......................................................................................... 84 6.9.1 Audio Widget Capabilities ..................................................................................................... 84 6.9.2 Pin Capabilities ...................................................................................................................... 85 6.9.3 Connection List Length .......................................................................................................... 85 6.9.4 Supported Power States ....................................................................................................... 86 6.9.5 Connection List Entry ............................................................................................................ 86 6.9.6 Power States ......................................................................................................................... 86 6.9.7 Pin Widget Control ................................................................................................................ 87 6.9.8 Unsolicited Response Control ............................................................................................... 88 6.9.9 Pin Sense .............................................................................................................................. 89 6.9.10 EAPD/BTL Enable ............................................................................................................... 89 6.9.11 Configuration Default ........................................................................................................... 90 6.10 Line Out 2 Pin Widget (Node ID = 0Bh) ....................................................................................... 91 6.10.1 Audio Widget Capabilities ................................................................................................... 91 6.10.2 Pin Capabilities .................................................................................................................... 92 6.10.3 Connection List Length ........................................................................................................ 92 6.10.4 Connection List Entry .......................................................................................................... 92 6.10.5 Pin Widget Control .............................................................................................................. 93 6.10.6 EAPD/BTL Enable ............................................................................................................... 94 6.10.7 Configuration Default ........................................................................................................... 95 6.11 Line In 1/Mic In 2, Mic In 1/Line In 2 Pin Widgets (Node ID = 0Ch, 0Dh) .................................... 96 6.11.1 Audio Widget Capabilities ................................................................................................... 96 6.11.2 Line In 1/Mic In 2 Pin Capabilities ....................................................................................... 97 6.11.3 Mic In 1/Line In 2 Pin Capabilities ....................................................................................... 97 6.11.4 Input Amplifier Capabilities .................................................................................................. 98 6.11.5 Supported Power States ..................................................................................................... 98 6.11.6 Power States ....................................................................................................................... 99 6.11.7 Line In 1/Mic In 2 Pin Widget Control ................................................................................ 100 6.11.8 Mic In 1/Line In 2 Pin Widget Control ................................................................................ 101 6.11.9 Unsolicited Response Control ........................................................................................... 101 6.11.10 Pin Sense ........................................................................................................................ 102 6.11.11 Mic In 1/Line In 2 EAPD/BTL Enable .............................................................................. 103 6.11.12 Line In 1/Mic In 2 Configuration Default .......................................................................... 103 6.11.13 Mic In 1/Line In 2 Configuration Default .......................................................................... 104 6.11.14 Amplifier Gain/Mute ......................................................................................................... 105 6.12 Digital Mic In 1, Digital Mic In 2 Pin Widgets (Node ID = 0Eh, 12h) ........................................... 107 6.12.1 Audio Widget Capabilities ................................................................................................. 107 6.12.2 Pin Capabilities .................................................................................................................. 108 6.12.3 Input Amplifier Capabilities ................................................................................................ 108 6.12.4 Pin Widget Control ............................................................................................................ 109 6.12.5 Digital Mic In 1 Configuration Default ................................................................................ 109 6.12.6 Digital Mic In 2 Configuration Default ................................................................................ 110 6.12.7 Amplifier Gain/Mute ........................................................................................................... 111 6.13 S/PDIF Receiver Input Pin Widget (Node ID = 0Fh) .................................................................. 113 6.13.1 Audio Widget Capabilities ................................................................................................. 113 6.13.2 Pin Capabilities .................................................................................................................. 114 6.13.3 Supported Power States ................................................................................................... 114 6.13.4 Power States ..................................................................................................................... 115 6.13.5 Pin Widget Control ............................................................................................................ 116 6.13.6 Unsolicited Response Control ........................................................................................... 116 DS880F1 5
CS4207
6.13.7 Pin Sense .......................................................................................................................... 117 6.13.8 Configuration Default ......................................................................................................... 118 6.14 S/PDIF Transmitter 1, S/PDIF Transmitter 2 Output Pin Widgets (Node ID = 10h, 15h) ........... 119 6.14.1 Audio Widget Capabilities ................................................................................................. 119 6.14.2 Pin Capabilities .................................................................................................................. 120 6.14.3 Connection List Length ...................................................................................................... 120 6.14.4 S/PDIF Transmitter 1 Connection List Entry ..................................................................... 121 6.14.5 S/PDIF Transmitter 2 Connection List Entry ..................................................................... 121 6.14.6 Pin Widget Control ............................................................................................................ 122 6.14.7 S/PDIF Transmitter 1 Configuration Default ...................................................................... 123 6.14.8 S/PDIF Transmitter 2 Configuration Default ...................................................................... 124 6.15 Vendor Processing Widget (Node ID = 11h) .............................................................................. 125 6.15.1 Audio Widget Capabilities ................................................................................................. 125 6.15.2 Processing Capabilities ..................................................................................................... 125 6.15.3 Processing State ............................................................................................................... 126 6.15.4 Coefficient Index ................................................................................................................ 126 6.15.5 Processing Coefficient ....................................................................................................... 127 6.15.6 Coefficient Registers ......................................................................................................... 127 6.15.6.1 S/PDIF RX/TX Interface Status (CIR = 0000h) ...................................................... 128 6.15.6.2 S/PDIF RX/TX Interface Control (CIR = 0001h) .................................................... 129 6.15.6.3 ADC Configuration (CIR = 0002h) ......................................................................... 130 6.15.6.4 DAC Configuration (CIR = 0003h) ......................................................................... 133 6.15.6.5 Beep Configuration (CIR = 0004h) ........................................................................ 134 6.16 Beep Generator Widget (Node ID = 13h) .................................................................................. 135 6.16.1 Audio Widget Capabilities ................................................................................................. 135 6.16.2 Beep Generation Control ................................................................................................... 136 7. APPLICATIONS ................................................................................................................................. 137 7.1 HD Audio Interface ....................................................................................................................... 137 7.1.1 Multi-Channel Streams ........................................................................................................ 137 7.2 Analog Outputs ............................................................................................................................ 137 7.2.1 Analog Supply Removal ...................................................................................................... 137 7.3 Digital Mic Inputs .......................................................................................................................... 137 8. ANALOG OUTPUT AND FILTERING ................................................................................................ 139 9. PCB LAYOUT CONSIDERATIONS ................................................................................................... 139 9.1 Power Supply, Grounding ............................................................................................................ 139 9.2 QFN Thermal Pad ........................................................................................................................ 140 10. PARAMETER DEFINITIONS ............................................................................................................ 140 11. PACKAGE DIMENSIONS ................................................................................................................ 141 THERMAL CHARACTERISTICS ....................................................................................................... 141 12. ORDERING INFORMATION ............................................................................................................ 142 13. REFERENCES .................................................................................................................................. 142 14. REVISION HISTORY ........................................................................................................................ 143
6
DS880F1
CS4207
LIST OF FIGURES
Figure 1.Typical Connection Diagram - Desktop System ......................................................................... 11 Figure 2.Typical Connection Diagram - Portable System ......................................................................... 12 Figure 3.Output Test Load, Headphone Out ............................................................................................. 18 Figure 4.Output Test Load, Line Out ......................................................................................................... 18 Figure 5.Output Test Load, Headphone Out ............................................................................................. 20 Figure 6.Output Test Load, Line Out ......................................................................................................... 20 Figure 7.Jack Presence Detect Circuit ...................................................................................................... 30 Figure 8.Software Programming Model .................................................................................................... 32 Figure 9.Differential to Single-Ended Output Filter ................................................................................. 139 Figure 10.Passive Single-Ended Output Filter ........................................................................................ 139
LIST OF TABLES
Table 1. Register Settings Across Reset Conditions ................................................................................ 28 Table 2. Device Node ID Summary ........................................................................................................... 33 Table 3. Pin Configuration Register Defaults ............................................................................................ 34
DS880F1
7
CS4207 1. PIN DESCRIPTIONS
1.1 CS4207 Pinout:
LINEOUT_R137
SPDIF_OUT1
VHP_FILT+
VHP_FILT-
HPOUT_R
48
47
46
45
44
43
42
41
40
39
VL_IF GPIO0/DMIC_SDA1 VL_HD DMIC_SCL SDO BITCLK DGND SDI VD SYNC RESET# GPIO1/DMIC_SDA2 /SPDIF_OUT2
HPOUT_L
38
SPDIF_IN
VA_HP
FLYC
FLYP
FLYN
HPREF
1 2 3 4 5 6
36 35 34 33 32 31
LINEOUT_R1+ LINEOUT_L1+ LINEOUT_L1LINEOUT_R2LINEOUT_R2+ LINEOUT_L2+ LINEOUT_L2VBIAS (DAC) VCOM VREF+ (ADC) AGND VA
Thermal Pad
7 8 9 10 11 12 30 29 28 27
Top-Down (Through Package) View 48-Pin QFN Package
26 25
HPREF
13
14
15
16
17
18
19
20
21
22
23
24
MICIN_L+
GPIO2
GPIO3
LINEIN_C-
MICIN_L-
MICIN_R-
Pin Name
VL_IF GPIO0/ DMIC_SDA1 VL_HD DMIC_SCL SDO BITCLK DGND SDI VD
#
1 2 3 4 5 6 7 8 9
Pin Description
Digital Interface Signal Level (Input) - Determines the required signal level for the GPIO, S/PDIF and Digital Mic interfaces. Refer to the Recommended Operating Conditions for appropriate voltages. General Purpose I/O (Input/Output) - General purpose input or output line, or Digital Mic Data Input (Input) - The second data input line from a digital microphone. Digital Interface Signal Level (Input) - Determines the required signal level for the HD Audio interface. Refer to the Recommended Operating Conditions for appropriate voltages. Digital Mic Clock (Output) - The high speed clock output to the digital microphone. Serial Data Input (Input) - Serial data input stream from the HD Audio Bus. Bit Clock (Input) - 24 MHz bit clock from the HD Audio Bus. Digital Ground (Input) - Ground reference for the internal digital section. Serial Data Output (Input/Output) - Serial data output stream to the HD Audio Bus. Digital Power (Input) - Positive power for the internal digital section.
8
LINEIN_R+
MICIN_R+
SENSE_A
MICBIAS
LINEIN_L+
VA_REF
DS880F1
CS4207
SYNC RESET# GPIO1/ DMIC_SDA2/ SPDIF_OUT2 SENSE_A GPIO2 GPIO3 MICBIAS MICIN_LMICIN_L+ MICIN_R+ MICIN_RLINEIN_L+ LINEIN_CLINEIN_R+ VA_REF VA AGND VREF+ VCOM VBIAS LINEOUT_L2LINEOUT_L2+ LINEOUT_R2+ LINEOUT_R2LINEOUT_L1LINEOUT_L1+ LINEOUT_R1+ LINEOUT_R1HPOUT_L HPREF HPOUT_R VHP_FILTFLYN FLYC VHP_FILT+ FLYP VA_HP SPDIF_IN SPDIF_OUT1 Thermal Pad 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 SYNC Clock (Input) - 48 kHz sync clock from the HD Audio Bus. Reset (Input) - The device enters a low power mode when this pin is driven low. General Purpose I/O (Input/Output) - General purpose input or output line, or Digital Mic Data Input (Input) - The second data input line from a digital microphone, or S/PDIF Output (Output) - Output from internal S/PDIF Transmitter. Jack Sense Pin (Input/Output) - Jack sense detect. General Purpose I/O (Input/Output) - General purpose input or output lines. General Purpose I/O (Input/Output) - General purpose input or output lines. Microphone Bias (Output) - Provides a low noise bias supply for an external microphone. Electrical characteristics are specified in the DC Electrical Characteristics table. Microphone Input Left/Right (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. Analog Input (Input) - The full-scale level is specified in the ADC Analog Characteristics specification table. Analog Power (Input) - Positive power for the internal analog section. VA_REF is the return pin for the VBIAS cap. Analog Ground (Input) - Ground reference for the internal analog section. Positive Voltage Reference (Output) - Positive reference voltage for the internal ADCs. Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. Positive Voltage Reference (Output) - Positive reference voltage for the internal DACs.
Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteristics specification table
Analog Headphone Output (Output) - The full-scale output level is specified in the DAC Analog Characteristics specification table. Pseudo Diff. Headphone Reference (Input) - Ground reference for the headphone amplifiers. Analog Headphone Output (Output) - The full-scale output level is specified in the DAC Analog Characteristics specification table. Inverting Charge Pump Filter Connection (Output) - Power supply from the inverting charge pump that provides the negative rail for the headphone amplifier. Charge Pump Cap Negative Node (Output) - Negative node for the inverting charge pump's flying capacitor. Charge Pump Cap Common Node (Output) - Common positive node for the step-down and inverting charge pumps' flying capacitor. Non-Inverting Charge Pump Filter Connection (Output) - Power supply from the step-down charge pump that provides the positive rail for the headphone amplifier. Charge Pump Cap Positive Node (Output) - Positive node for the step-down charge pump's flying capacitor. Analog Power For Headphone (Input) - Positive power for the internal analog headphone section. S/PDIF Input (Input) - Input to internal S\PDIF Receiver. S/PDIF Output (Output) - Output from internal S/PDIF Transmitter. HP Ground (Thermal Pad) - Ground reference for the internal headphone section.
DS880F1
9
CS4207
1.2 Digital I/O Pin Characteristics
Input and output levels and associated power supply voltage are shown in the table below. Logic levels should not exceed the corresponding power supply voltage. Power Supply Pin Name SW/(HW)
RESET# SDO BITCLK SDI (Note 1) SYNC SENSE_A GPIO1/ DMIC_SDA2 GPIO2 GPIO3 SPDIF_IN SPDIF_OUT GPIO0/ DMIC_SDA1 DMIC_SCL
I/O
Input Input Input Input/Output Input Input Input/Output Input/Output Input/Output Input Output Input/Output Output
Driver
1.5 V - 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
Receiver
1.5 V - 3.3 V 1.5 V - 3.3 V 1.5 V - 3.3 V 1.5 V - 3.3 V 1.5 V - 3.3 V 3.3 V - 5.0 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V -
VL_HD
VA
VL_IF
Notes: 1. SDI output functionality also requires the VA and VL_IF rails to be at nominal levels.
10
DS880F1
CS4207 2. TYPICAL CONNECTION DIAGRAMS
+5.0 V
0.1 F 0.1 F
+1.8 V
VA +5.0 V
0.1 F
VD
+
VA_REF
10 F
HPOUT_L VBIAS HPREF HPOUT_R
Left Headphone
33 0.1 F
+5.0 V
VA_HP
CS4207
Headphone Ground Right Headphone
33 0.1 F
VHP_FILT+ VHP_FILT0.1 F ** F ** F 10 10
LINEOUT_L1+ FLYP
** 2.2 F
LINEOUT_L1-
Differential to Single-Ended Output Filter Differential to Single-Ended Output Filter Differential to Single-Ended Output Filter Differential to Single-Ended Output Filter
+Left Line Output 1
FLYC
** 2.2 F
LINEOUT_R1+ LINEOUT_R1LINEOUT_L2+
FLYN
** Use low ESR ceramic capacitors.
+Right Line Output 1
+Left Line Output 2
BITCLK SYNC HD Audio Bus SDI SDO RESET +1.5 V to +3.3 V VL_HD
0.1 F
LINEOUT_L2LINEOUT_R2+ LINEOUT_R2-
+Right Line Output 2
* Capacitors must be C0G or equivalent
LINEIN_L+
1 F
*
1800 pF 1 F
Left Analog Input
LINEIN_C+3.3 V
0.1 F
VL_IF
LINEIN_R+
1 F
*
1800 pF
Right Analog Input
GPIO2 GPIO3 SENSE_A
GPIO2 GPIO3 SENSE_A MICIN_L+
1 F
MICIN_L1 F
Differential Mic Left Microphone Bias
S/PDIF RX S/PDIF TX 1 D-Mic In 2 / S/PDIF TX 2
SPDIF_IN SPDIF_OUT1 DMIC_SDA2/ SPDIF_OUT2
MICBIAS
0.47 F
RL RL
The value of R L is dictated by the microphone cartridge.
MICIN_R+
1 F
Differential Mic Right
D-Mic In 1 D-Mic Clk
DMIC_SDA1 DMIC_SCL
MICIN_R1 F
VCOM VREF+
1 F 10 F
Input and Output filters are optional.
AGND HP_GND(Thermal Pad)
Figure 1. Typical Connection Diagram - Desktop System DS880F1 11
CS4207
+3.3 V
0.1 F 0.1 F
+1.8 V
VA +3.3 V
0.1 F
VD
+
VA_REF
10 F
HPOUT_L VBIAS HPREF HPOUT_R
Left Headphone
33 0.1 F
+3.3 V
VA_HP
CS4207
Headphone Ground Right Headphone
33 0.1 F
VHP_FILT+ VHP_FILT0.1 F ** F ** F 10 10
LINEOUT_L1+ FLYP LINEOUT_L1-
** 2.2 F
FLYC
** 2.2 F
LINEOUT_R1+ LINEOUT_R1LINEOUT_L2+
FLYN
* *Use low ESR ceramic capacitors.
560
* 2200 pF
BITCLK SYNC HD Audio Bus SDI SDO RESET +1.5 V to +3.3 V VL_HD
0.1 F
LINEOUT_L2-
560
Speaker Driver
LINEOUT_R2+
560
* 2200 pF
LINEOUT_R2-
560
Speaker Driver
* Capacitors must be C0G or equivalent
LINEIN_L+
1 F
*
1800 pF 1 F
Left Analog Input
+3.3 V
0.1 F
VL_IF
LINEIN_CLINEIN_R+
1 F
*
1800 pF
Right Analog Input
GPIO2 GPIO3 SENSE_A
GPIO2 GPIO3 SENSE_A MICIN_LMICIN_L+
1 F
Left Mic In Microphone Bias
S/PDIF RX S/PDIF TX 1 D-Mic In 2 / S/PDIF TX 2
SPDIF_IN SPDIF_OUT1 DMIC_SDA2/ SPDIF_OUT2
MICBIAS
0.47 F
RL RL
The value of R L is dictated by the microphone cartridge.
MICIN_R+
1 F
Right Mic In
MICIN_RD-Mic In 1 D-Mic Clk DMIC_SDA1 DMIC_SCL VCOM VREF+
1 F 10 F
AGND HP_GND(Thermal Pad)
Figure 2. Typical Connection Diagram - Portable System
12 DS880F1
CS4207 3. CHARACTERISTIC AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS
(AGND=DGND=0 V, all voltages with respect to ground.)
Parameters
DC Power Supply (Note 1) Analog Core DAC Reference Headphone Amplifier Digital Core HD Audio Bus Interface GPIO, S/PDIF and Digital Mic Interface Ambient Temperature
Symbol
VA VA_REF VA_HP VD VL_HD VL_IF Commercial - CNZ Automotive - DNZ TA
Min
2.97 2.97 2.97 1.42 1.42 2.97 -40 -40
Max
5.25 5.25 5.25 1.89 3.47 3.47 +85 +105
Units
V V V V V V C C
ABSOLUTE MAXIMUM RATINGS
(AGND = DGND = 0 V; all voltages with respect to ground.)
Parameters
Analog Core DAC Reference Headphone Amplifier Digital Core HD Audio Interface GPIO, S/PDIF and Digital Mic Interface Input Current (Note 2) Analog Input Voltage (Note 3) Digital Input Voltage (Note 3)HD Audio Interface GPIO, S/PDIF and Digital Mic Interface Ambient Operating Temperature (power applied) Storage Temperature DC Power Supply
Symbol VA VA_REF VA_HP VD VL_HD VL_IF Iin
VIN
VIND TA Tstg
Min Max 5.5 -0.3 5.5 -0.3 5.5 -0.3 3.0 -0.3 4.0 -0.3 4.0 -0.3 10 AGND-0.7 VA+0.7 -0.3 VL_HD+0.4 -0.3 VL_IF+0.4 -55 +115 -65 +150
Units V V V V V V mA
V
V V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes:
1. The device will operate properly over the full range of the analog, digital and interface supplies. 2. Any pin except supplies. Transient currents of up to 100 mA on the analog input pins will not cause SCR latch-up. 3. The maximum over/under voltage is limited by the input current.
DS880F1
13
CS4207 ANALOG INPUT CHARACTERISTICS (COMMERCIAL - CNZ)
(Test Conditions (unless otherwise specified): Input sine wave (relative to digital full-scale): 1 kHz through passive input filter; VA_HP = VA; VL_HD = VL_IF = 3.3; VD = 1.8 V; TA = +25C; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz)
VA, VA_REF = 5.0 V VA, VA_REF = 3.3 V (Differential/Single-ended) (Differential/Single-ended) Parameter (Note 4) Min Typ Max Min Typ Max Unit Line In to PGA to ADC (ADC1 or ADC2; differential perf. characteristics only valid for ADC2) Dynamic Range PGA Setting: 0 dB A-weighted 99/96 105/102 95/93 101/99 dB unweighted 96/93 102/99 92/90 98/96 dB PGA Setting: +12 dB A-weighted 95/86 101/92 92/83 98/89 dB unweighted 92/83 98/89 89/80 95/86 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS -88/-88 -82/-82 -95/-92 -89/-86 dB -60 dBFS -42/-39 -36/-33 -38/-36 -32/-30 dB PGA Setting: +12 dB -1 dBFS -88/-88 -82/-82 -92/-86 -86/-80 dB Mic In to PGA to ADC (+20dB) (ADC1 or ADC2; differential perf. characteristics only valid for ADC2) Dynamic Range A-weighted 86/78 92/84 83/75 89/81 dB unweighted 83/75 89/81 80/72 86/78 dB Total Harmonic Distortion + Noise -1 dBFS -89/-82 -83/-76 -86/-78 -80/-72 dB Other Analog Characteristics DC Accuracy Interchannel Gain Mismatch 0.2 0.2 dB ppm/C Gain Drift 100 100 Offset Error High Pass Filter On 352 352 LSB Interchannel Isolation 90 90 dB HP Amp to Analog Input Isolation RL = 10 k 100 100 dB 70 70 dB RL = 16
Full-scale Input Voltage - Line In/Mic In (Differential Inputs) PGA(0dB) 1.58*VA Full-scale Input Voltage - Line In
(Single-ended Inputs) PGA(0dB) PGA(+12dB)
1.66*VA 0.83*VA 0.21*VA 0.83*VA 0.08*VA 40/20 60
1.74*VA 0.87*VA
1.58*VA 0.79*VA
1.66*VA 0.83*VA 0.21*VA 0.83*VA 0.08*VA 40/20 60
1.74*VA 0.87*VA
Vpp Vpp Vpp Vpp Vpp k dB
0.79*VA
Full-scale Input Voltage - Mic In
PGA+Boost(0dB) (Single-ended Inputs) PGA+Boost(+20dB)
0.79*VA -
0.87*VA -
0.79*VA -
0.87*VA -
Input Impedance (Note 5) Common Mode Rejection (Differential Inputs)
4. Referred to the typical full-scale voltage. Applies to all THD+N and Dynamic Range values in the table. 5. Measured between Line/Mic In for differential inputs and +Line/Mic In and AGND for single-ended.
14
DS880F1
CS4207 ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE - DNZ)
(Test Conditions (unless otherwise specified): Input sine wave (relative to digital full-scale): 1 kHz through passive input filter; VA_HP = VA; VL_HD = VL_IF = 3.3; VD = 1.8 V; TA = -40 to +85C; Measurement Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Sample Frequency = 48 kHz)
VA, VA_REF = 5.0 V VA, VA_REF = 3.3 V (Differential/Single-ended) (Differential/Single-ended) Parameter (Note 4) Min Typ Max Min Typ Max Unit Line In to PGA to ADC (ADC1 or ADC2; differential perf. characteristics only valid for ADC2) Dynamic Range PGA Setting: 0 dB A-weighted 99/96 105/102 95/93 101/99 dB unweighted 96/93 102/99 92/90 98/96 dB PGA Setting: +12 dB A-weighted 95/86 101/92 92/83 98/89 dB unweighted 92/83 98/89 89/80 95/86 dB Total Harmonic Distortion + Noise PGA Setting: 0 dB -1 dBFS -88/-88 -82/-82 -95/-92 -89/-86 dB -60 dBFS -42/-39 -36/-33 -38/-36 -32/-30 dB PGA Setting: +12 dB -1 dBFS -88/-88 -82/-82 -92/-86 -86/-80 dB Mic In to PGA to ADC (+20dB) (ADC1 or ADC2; differential perf. characteristics only valid for ADC2) Dynamic Range A-weighted 86/78 92/84 83/75 89/81 dB unweighted 83/75 89/81 80/72 86/78 dB Total Harmonic Distortion + Noise -1 dBFS -89/-82 -83/-76 -86/-78 -80/-72 dB Other Analog Characteristics DC Accuracy Interchannel Gain Mismatch 0.2 0.2 dB ppm/C Gain Drift 100 100 Offset Error High Pass Filter On 352 352 LSB Interchannel Isolation 90 90 dB HP Amp to Analog Input Isolation RL = 10 k 100 100 dB 70 70 dB RL = 16
Full-scale Input Voltage - Line In/Mic In PGA(0dB) 1.58*VA (Differential Inputs) Full-scale Input Voltage - Line In
(Single-ended Inputs) PGA(0dB) PGA(+12dB)
1.66*VA 0.83*VA 0.21*VA 0.83*VA 0.08*VA 40/20 60
1.74*VA 0.87*VA
1.58*VA 0.79*VA
1.66*VA 0.83*VA 0.21*VA 0.83*VA 0.08*VA 40/20 60
1.74*VA 0.87*VA
Vpp Vpp Vpp Vpp Vpp k dB
0.79*VA
Full-scale Input Voltage - Mic In
PGA+Boost(0dB) (Single-ended Inputs) PGA+Boost(+20dB)
0.79*VA -
0.87*VA -
0.79*VA -
0.87*VA -
Input Impedance (Note 5) Common Mode Rejection (Differential Inputs)
6. Referred to the typical full-scale voltage. Applies to all THD+N and Dynamic Range values in the table. 7. Measured between Line/Mic In for differential inputs and +Line/Mic In and AGND for single-ended.
DS880F1
15
CS4207 ADC DIGITAL FILTER CHARACTERISTICS
Parameter (Note 8) Passband (Frequency Response) Passband Ripple Stopband Stopband Attenuation Total Group Delay High-Pass Filter Characteristics (48 kHz Fs) Frequency Response -3.0 dB -0.13 dB Phase Deviation @ 20 Hz Passband Ripple Filter Settling Time Min 0 -0.09 0.6 70 -
to -0.1 dB corner
Typ 7.6/Fs
3.6 24.2 10 105/Fs
Max .4535 0.17 0.17 0
Unit Fs dB Fs dB s
Hz Hz Deg dB s
8. Response is clock-dependent and will scale with Fs.
DIGITAL MICROPHONE CHARACTERISTICS
Parameter
DMIC_SCL Period DMIC_SCL Period FsADC >= 44.1 kHz FsADC <= 32.0 kHz
Min
-
Typ
8 * TBITCLK 12 * TBITCLK
Max
-
Unit
s s
16
DS880F1
CS4207 ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ)
(Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; VD = 1.8 V; VL_HD = VL_IF = 3.3V; TA = +25C; Measurement bandwidth is 10 Hz to 20 kHz; test load RL = 10 k, CL = 10 pF for the line output and test load RL = 16 , CL = 10 pF for the headphone output (see Figure 3); DAC Gain = 0 dB).
Parameter (Note 4) DAC1; RL = 16 ; DAC Gain = -5 dB
A-weighted unweighted 16-Bit A-weighted unweighted Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB DAC1; RL = 10 k Dynamic Range 18 to 24-Bit Dynamic Range 18 to 24-Bit
VA, VA_REF = 5.0 V VA_HP = 5.0 V (Single-ended) Min Typ Max
VA, VA_REF = 3.3 V VA_HP = 3.3 V (Single-ended) Min Typ Max
Unit
95 92 -
101 98 93 90 -89 -78 -38 -89 -70 -30
-83 -72 -32 -
93 90 -
99 96 93 90 -93 -76 -36 -90 -70 -30
-87 -70 -30 -
dB dB dB dB dB dB dB dB dB dB
106 100 A-weighted 103 97 unweighted 96 16-Bit A-weighted 93 unweighted Total Harmonic Distortion + Noise -88 18 to 24-Bit 0 dB -83 -20 dB -43 -60 dB -88 16-Bit 0 dB -73 -20 dB -33 -60 dB Other Characteristics for DAC1; RL = 16 or 10 k Full-scale Output Voltage, RL = 10 k
Output Power, THD+N = -75 dB, RL = 16
-82 -77 -37 0.88*VA 0.25 4 150 -
98 95 0.80*VA 16 -
104 101 96 93 -90 -81 -41 -90 -73 -33 0.84*VA 17 23 35 80 93 0.1 2 100 300
-84 -75 -35 0.88*VA 0.25 4 150 -
dB dB dB dB dB dB dB dB dB dB Vpp mWrms mWrms mWrms dB dB dB mV ppm/C pF m
0.80*VA 16 -
0.84*VA 38 50 74 80 95 0.1 2 100 300
Output Power, THD+N = 1%, RL = 16 Output Power,THD+N = 10%, RL = 16 Interchannel Isolation (1 kHz) 16 10 k
Interchannel Gain Mismatch Output Offset Voltage DAC to HPOUT Gain Drift AC-Load Resistance (RL) (Note 10) Load Capacitance (CL) Output Impedance (Note 10)
DS880F1
17
CS4207
VA, VA_REF = 5.0 V (Differential/Single-ended) Min Typ Max VA, VA_REF = 3.3 V (Differential/Single-ended) Min Typ Max
Parameter (Note 4)
DAC2/DAC3; RL = 10 k Dynamic Range 18 to 24-Bit
Unit
A-weighted 104/100 110/106 unweighted 101/97 107/103 96 16-Bit A-weighted 93 unweighted Total Harmonic Distortion + Noise -94/-91 18 to 24-Bit 0 dB -87/-83 -20 dB -47/-43 -60 dB -92 16-Bit 0 dB -73 -20 dB -33 -60 dB Other Characteristics for DAC2/DAC3; RL = 10 k Full-scale Output Voltage
-88/-85 -81/-77 -41/-37 -
101/97 98/94 -
107/103 104/100 96 93 -96/-94 -84/-80 -44/-40 -92 -73 -33
-90/-88 -78/-74 -38/-34 -
dB dB dB dB dB dB dB dB dB dB Vpp dB dB ppm/C k pF
1.60*VA/ 1.68*VA/ 1.76*VA/ 1.60*VA/ 1.68*VA/ 1.76*VA/ 0.80*VA 0.84*VA 0.88*VA 0.80*VA 0.84*VA 0.88*VA Interchannel Isolation (1 kHz) 100 100 Interchannel Gain Mismatch 0.1 0.25 0.1 0.25 Gain Drift 100 100 AC-Load Resistance (RL) (Note 10) 3 3 (Note 10) 100 100 100 100 -
Load Capacitance (CL) Output Impedance
9. One-half LSB of triangular PDF dither is added to data. 10. See Figure 3. RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity.
HPOUT_L/R
33
LINEOUT_L/R
C L R L
C
L
R
L
0.1 F
AGND
AGND
Figure 3. Output Test Load, Headphone Out
Figure 4. Output Test Load, Line Out
18
DS880F1
CS4207 ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ)
(Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; VD = 1.8 V; VL_HD = VL_IF = 3.3V; TA = -40 to +85C; Measurement bandwidth is 10 Hz to 20 kHz; test load RL = 10 k, CL = 10 pF for the line output and test load RL = 16 , CL = 10 pF for the headphone output (see Figure 3); DAC Gain = 0 dB).
Parameter (Note 4) DAC1; RL = 16 ; DAC Gain = -5 dB
A-weighted unweighted 16-Bit A-weighted unweighted Total Harmonic Distortion + Noise 18 to 24-Bit 0 dB -20 dB -60 dB 16-Bit 0 dB -20 dB -60 dB DAC1; RL = 10 k Dynamic Range 18 to 24-Bit Dynamic Range 18 to 24-Bit
VA, VA_REF = 5.0 V VA_HP = 5.0 V (Single-ended) Min Typ Max
VA, VA_REF = 3.3 V VA_HP = 3.3 V (Single-ended) Min Typ Max
Unit
95 92 -
101 98 93 90 -89 -78 -38 -89 -70 -30
-83 -72 -32 -
93 90 -
99 96 93 90 -93 -76 -36 -90 -70 -30
-87 -70 -30 -
dB dB dB dB dB dB dB dB dB dB
106 100 A-weighted 103 97 unweighted 96 16-Bit A-weighted 93 unweighted Total Harmonic Distortion + Noise -88 18 to 24-Bit 0 dB -83 -20 dB -43 -60 dB -88 16-Bit 0 dB -73 -20 dB -33 -60 dB Other Characteristics for DAC1; RL = 16 or 10 k Full-scale Output Voltage, RL = 10 k
Output Power, THD+N = -75 dB, RL = 16
-82 -77 -37 0.88*VA 0.25 5 150 -
98 95 0.80*VA 16 -
104 101 96 93 -90 -81 -41 -90 -73 -33 0.84*VA 17 23 35 80 93 0.1 2 100 300
-84 -75 -35 0.88*VA 0.25 5 150 -
dB dB dB dB dB dB dB dB dB dB Vpp mWrms mWrms mWrms dB dB dB mV ppm/C pF m
0.80*VA 16 -
0.84*VA 38 50 74 80 95 0.1 2 100 300
Output Power, THD+N = 1%, RL = 16 Output Power,THD+N = 10%, RL = 16 Interchannel Isolation (1 kHz) 16 10 k
Interchannel Gain Mismatch Output Offset Voltage DAC to HPOUT Gain Drift AC-Load Resistance (RL) (Note 10) Load Capacitance (CL) Output Impedance (Note 10)
DS880F1
19
CS4207
VA, VA_REF = 5.0 V (Differential/Single-ended) Min Typ Max VA, VA_REF = 3.3 V (Differential/Single-ended) Min Typ Max
Parameter (Note 4)
DAC2/DAC3; RL = 10 k Dynamic Range 18 to 24-Bit
Unit
A-weighted 104/100 110/106 unweighted 101/97 107/103 96 16-Bit A-weighted 93 unweighted Total Harmonic Distortion + Noise -94/-91 18 to 24-Bit 0 dB -87/-83 -20 dB -47/-43 -60 dB -92 16-Bit 0 dB -73 -20 dB -33 -60 dB Other Characteristics for DAC2/DAC3; RL = 10 k Full-scale Output Voltage
-88/-85 -81/-77 -41/-37 -
101/97 98/94 -
107/103 104/100 96 93 -96/-94 -84/-80 -44/-40 -92 -73 -33
-88/-88 -78/-74 -38/-34 -
dB dB dB dB dB dB dB dB dB dB Vpp dB dB ppm/C k pF
1.60*VA/ 1.68*VA/ 1.76*VA/ 1.60*VA/ 1.68*VA/ 1.76*VA/ 0.80*VA 0.84*VA 0.88*VA 0.80*VA 0.84*VA 0.88*VA Interchannel Isolation (1 kHz) 100 100 Interchannel Gain Mismatch 0.1 0.25 0.1 0.25 Gain Drift 100 100 AC-Load Resistance (RL) (Note 10) 3 3 (Note 10) 100 100 100 100 -
Load Capacitance (CL) Output Impedance
11. One-half LSB of triangular PDF dither is added to data. 12. See Figure 3. RL and CL reflect the recommended minimum resistance and maximum capacitance required for the internal op-amp's stability and signal integrity.
HPOUT_L/R
33
LINEOUT_L/R
C L R L C L R L
0.1 F
AGND
AGND
Figure 5. Output Test Load, Headphone Out
Figure 6. Output Test Load, Line Out
20
DS880F1
CS4207 COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
Parameter
Frequency Response 10 Hz to 20 kHz Passband StopBand StopBand Attenuation (Note 13) Total Group Delay 13. Measurement Bandwidth is from Stopband to 100 kHz. to -0.01 dB corner to -3 dB corner
Min
-0.01 0 0 -
Typ 26256 102 0.196
Max
+0.01 21792 23952 -
Unit dB Hz Hz Hz dB ms
DC ELECTRICAL CHARACTERISTICS
(AGND = 0 V; all voltages with respect to ground.)
Parameters
VCOM Characteristics Nominal Voltage Output Impedance DC Current Source/Sink (Note 14) VHP_FILT+ Characteristics Nominal Voltage VHP_FILT- Characteristics Nominal Voltage MIC BIAS Characteristics Nominal Voltage VREFE = 000b VREFE = 001b VREFE = 010b VREFE = 100b (VA=5.0V) (VA=3.3V) 1 kHz
Min
-
Typ
0.5*VA 23 0.5*VA_HP -0.5*VA_HP Hi-Z 0.5*VA GND 0.8*VA 5 3 60
Max
10 -
Units
V k A V V V V V V mA mA dB
DC Current Source Power Supply Rejection Ratio (PSRR) (Note 15)
14. The DC current draw represents the allowed current draw from the VCOM pin due to typical leakage through electrolytic de-coupling capacitors. 15. Valid with the recommended capacitor values on VBIAS. Increasing the capacitance will also increase the PSRR.
DS880F1
21
CS4207 DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS
Parameters (Note 16) Input Leakage Current Input Pin Capacitance VL_HD = 1.5 V High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (IOUT = -500 A)
Low-Level Output Voltage (IOUT = 1500 A) VL_HD = 3.3 V High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (IOUT = -500 A) Low-Level Output Voltage (IOUT = 1500 A) VL_IF = 3.3 V High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage (IOH = -100 A) Low-Level Output Voltage (IOL = 100 A) VIH VIL VOH VOL 0.65*VL_IF VL_IF - 0.2 0.35*VL_IF 0.2 V V V V VIH VIL VOH VOL 0.65*VL_HD 0.90*VL_HD 0.35*VL_HD 0.10*VL_HD V V V V
Symbol Iin Cin
VIH VIL VOH VOL
Min 0.60*VL_HD 0.90*VL_HD -
Max 10 7.5
0.40*VL_HD 0.10*VL_HD
Units A pF
V V V V
16. See "Digital I/O Pin Characteristics" on p 10 for HD Audio I/F and control power rails.
HD AUDIO BUS SPECIFICATIONS & CHARACTERISTICS
Parameter
BITCLK Period BITCLK High Time BITCLK Low Time BITCLK Jitter SDI Valid After BITCLK Rising SDO Setup Time SDO Hold Time TTCO TSU TH 3 5 5
Symbol TCYC THIGH TLOW
Min 41.163 17.50 17.50
Typ 41.67
150
Max 42.171 24.16 24.16 500 11
Units ns ns ns ps ns ns ns
S/PDIF TRANSMITTER/RECEIVER SPECIFICATIONS & CHARACTERISTICS
Parameter Transmitter Specifications & Characteristics AES3 Transmitter Output Jitter Receiver Specifications & Characteristics PLL Clock Recovery Sample Rate Range Input Jitter Tolerance Symbol
TJIT(rms) frec TJIT(rms) meets IEC 60958-3
Min
Typ
Max
Units
ps kHz ps
meets IEC 60958-3
22
DS880F1
CS4207 POWER CONSUMPTION
(This table represents the power consumption for individual circuit blocks within the CODEC) (See (Note 17))
Typical Current (mA)
iVA iVA_HP iVD VD =1.8V iVL_HD VL_HD =3.3V iVL_IF VL_IF =3.3V
Individual Block Operation VA/ VA_HP 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
Total Power for individual block (mW)
9.35 12.24 31.70 44.80 57.57 95.12 51.27 83.84 19.78 22.51 25.91 28.64
1 response capable(Note 18)
Codec D3 State- unsolicited ADC1 or ADC2 with PGA operDAC1 with Headphone/Line DAC2 or DAC3 with DifferenS/PDIF transmitter with SRC S/PDIF receiver with SRC
2 ation and Pseudo-Diff Inputs 3 Out(Note 20)
4 tial Line Out(Note 21) 5 function 6 function
0.94 1.20 5.47 6.23 11.08 14.06 10.72 13.59 0.84 1.10 0.84 1.10
0.00 0.00 0.00 0.00 1.51 1.76 0.00 0.00 0.00 0.00 0.00 0.00
3.34 7.27 8.79 8.72 8.90 12.67
0.07 0.17 0.06 0.06 0.07 0.10
0.00 0.00 0.00 0.00 0.23 0.00
17. Unless otherwise noted, test conditions are as follows: All zeros input, sample rate = 48 kHz; No load. 18. RESET held HI, all HDA Bus clocks and data lines are running; HDA Interface running with support for unsolicited responses; All converters are in D3 state. 19. Represents total power for the HDA Bus interface logic playing 6 channels and capturing 4 channels of 48 kHz audio. 20. Full-scale single-ended output signal into a 10 k load. 21. Full-scale differential output signal into a 10 k load. (The following table demonstrates the total power consumption for typical system operation. These total CODEC power numbers are derive from the individual block power consumption numbers in the previous table.)
Power States
S/PDIF_OUT S/PDIF_IN
ADC1
ADC2
DAC1
DAC2
DAC3
Typical CODEC Operation
1 1 (PGA/ADC1)
Stereo Record from Line In Stereo Playback to HeadStereo Playback to Head-
D0 D3 D3 D3 D3 D3 D3 D3 D3 D0 D3 D3 D3 D3
2 phone (No Load)
3 phone Out and S/PDIF Out D3 D3 D0 D3 D3 D0 D3 4 Playback to S/PDIF Out 5 Line In 1 / Line Out 1
Receive from S/PDIF and Stereo Record & Playback D3 D3 D3 D3 D3 D0 D0 D0 D3 D3 D0 D3 D3 D3
CODEC VA/ Power (mW) VA_HP 3.3 41.04 HDA Interface + unsolicited response + ADC1 5.0 57.04 3.3 66.91 HDA Interface + unsolicited response + DAC1 5.0 107.36 3.3 86.69 HDA Interface + unsolicited response + DAC1+ S/PDIF OUT 5.0 129.87 3.3 55.04 HDA Interface + unsolicited response + S/PDIF IN/OUT 5.0 63.39 3.3 92.31 HDA Interface + unsolicited response + ADC1 + DAC2 5.0 140.88
Active Blocks
Total
DS880F1
23
CS4207 4. CODEC RESET AND INITIALIZATION
4.1 Link Reset
A Link Reset is a system controller generated assertion of the HD Audio Bus RESET signal. A Link reset will cause some of the HD Audio bus interface logic to be initialized. Following a Link Reset, the CS4207 will perform the Codec Initialization request sequence. Many of the codec settings will remain unchanged following a Link Reset. See "Register Settings Across Reset Conditions" section on page 28 for more details. When the codec has detected a Link Reset condition, all converter widgets and pin widgets will transition to a low power operating mode, if previously in D0. The actual power states reported will remain unchanged, i.e. if in D0 or D3 prior to Link Reset, the widget stays in D0 or D3. If enabled, presence detection will continue to sense any impedance changes and issue a power state change request to the Link prior to asserting an Unsolicited Response.
4.2
Function Group Reset
Because the CS4207 supports the Extended Power State Support (EPSS), a single occurrence of the Function Group Reset command will NOT cause the Audio Function unit and all associated widgets to initialize to the power-on reset values (as described in the HD Audio Specification, Rev. 1.0). When the CS4207 receives a single Function Group Reset verb, the codec will issue a response to the verb to acknowledge receipt, and reset each input/output converter widget's Stream Number and Lowest Channel Number to the default (0h). No other settings are modified. See "Register Settings Across Reset Conditions" section on page 28 for more details. The CS4207 will respond to the newly created "Double Function Group Reset" (as defined in HDA015-B, March 1, 2007) and will reset most of the register settings to their power on defaults. This "Double Function Group Reset" will not affect the HD Audio bus interface logic or the unique codec physical address, which must be reset with the link RESET signal. Therefore, the codec will not initiate a Codec Initialization sequence on the link. In addition, the Configuration Default settings will not be reset with a "Double Function Group Reset". This new reset condition is created by sending two Function Group resets back to back. The "Double Function Group Reset" is defined as two (2) Function Group Reset verbs received without any other intervening verbs. The Function Group Reset verbs are not required to be received in sequential frames, but there must not be any other verbs received in frames between the receipt of the Function Group Reset verbs. There are no implied time outs between the time the first Function Group Reset is received and the second Function Group Reset verb.
4.3
Codec Initialization
Immediately following the completion of a Link Reset sequence, the CS4207 will initiate a codec initialization sequence. The purpose of this initialization sequence is to acquire a unique address by which the codec can thereafter be referenced with Commands on the SDO signal. During this sequence, the Controller provides the codec with a unique address using its attached SDI signal. If the CS4207 codec is in a low power D3 state and enabled to support a presence detect event, it will retain its unique address while in that low power state. If RESET is de-asserted high, and BITCLK and SYNC are running at the time of a presence detect event, the codec will signal an unsolicited response. When put into the D3 low power state and enabled to support a presence detect event, with the link in the reset state (RESET is asserted low), the CS4207 will post the occurrence of a wake event and request a power state change by signaling a power state change request and initialization request. It will reestablish the connection with the controller by performing a "Codec Initialization request".
24
DS880F1
CS4207
If RESET is asserted low, and BITCLK and SYNC are not running at the time (defined as link low power state), the codec will signal the power state change request and initialization request asynchronously by asserting SDI high continuously until it detects the de-assertion of RESET. It will then asynchronously drive SDI low with the de-assertion of the RESET. With the RESET signal high, the codec will reestablish the connection with the controller by performing a "Codec Initialization request".
4.4
D3 Lower Power State Support
The D3 low power state allows for, but does not require, the lowest possible power consuming state under software control, in which Extended Power States Supported (EPSS) requirements can be met. While in the D3 state, the CS4207 will retain sufficient operational capability to properly respond to subsequent software Get/Set Power State commands (Verb ID=F05h/705h) to the Audio Function Group (Node ID = 01h). In addition, while in the D3 power state, Link Reset and "Double Function Group" reset are supported. All other Get/Set commands will be ignored while the codec is in the D3 power state. Widgets reporting an EPSS of `1'b will transition from D3 state to D0 state in less than 10 milliseconds (this is a target). This interval is measured from the response to the Set Power State verb that caused the transition from D3 back to fully operational D0 state. It is permissible for the audio fidelity for analog outputs to be slightly degraded if audio playback begins immediately once the fully operational state is entered. However, audio fidelity will not be degraded 75ms after the transitioning to D0 state.
4.5
Extended Power States Supported (EPSS)
EPSS indicates that the Audio Function Group or a particular Widget supports additional capabilities allowing better low power operation. The CS4207 will report EPSS support at the Function group level and will enable low power operation for all Input and Output Converter Widgets, and the following pin widgets which are capable of reporting presence detection:
- - - - - Headphone pin widget (node ID 09h) Line Out 1 pin widget (node ID 0Ah) Line In 1/Mic In 2 pin widget (node ID 0Ch) Mic In 1/Line In 2 pin widget (node ID 0Dh) S/PDIF Receiver Input pin widget (node ID 0Fh).
The following requirements will also be implemented by each input/output converter widget and the above listed pin widgets: * * * * Report PowerCntrl set to `1'b and support the Supported Power States verb. Jack Presence state change reporting (when enabled) will operate regardless of the Widget and Audio Function Group power state. Reporting of presence state change and issuing system wake when the link clock (BITCLK) is not operational is supported. The S/PDIF Receiver to S/PDIF Transmitter digital loop-through (no clock re-timing) will continue to operate (if enabled) even though any one, or all of the S/PDIF Receiver Input Converter Widget, S/PDIF Transmitter Output Converter Widget or S/PDIF Receiver Input Pin Widget enters into low power states. This digital loop-through will also continue to operate if the Audio Function Group is placed in the D3 low power state, during a Link Reset, and even if the HD Audio BITCLK is stopped. Dependencies between converter widgets and associated pin widgets will not cause unexpected results when one node of the dependency is placed into D3 state. The diagrams and tables below demonstrate typical audio streams.
*
DS880F1
25
CS4207
.
DAC Output Converter Widget D0/D3 Power States HD_Audio Bus ADC Input Converter Widget D0/D3 Power States Line In Input Pin Widget D0/D3 Power States LineOut Output Pin Widget D0/D3 Power States
Output Path
Output Pin Widget D0
*
Output Pin Widget D3
Converter widget continues to accept audio samples from the HD Audio bus. Pin widget outputs a muted audio signal, supports presence detect if enabled and transitions to D3.
Output Converter Widget D0
*
Normal Operation in D0
*
*
Output Converter Widget D3
*
Converter widget stops accepting audio samples from the HD Audio bus, sends mute * to the Pin widget and transitions to D3. Pin widget outputs a muted audio signal and supports presence detect if enabled. Remains in D0 state.
Converter and Pin Widgets are in low power D3 state. Supports presence detect if enabled.
Input Path
Input Pin Widget D0
Input Converter Widget D0
*
Normal Operation in D0
Input Pin Widget D3 * Converter widget will send "muted" audio samples to the HD Audio bus. Remains in D0 state.
* Pin widget outputs a muted audio signal, supports presence detect if enabled and transitions to D3.
*
Input Converter Widget D3
*
Converter widget stops sending audio samples to the HD Audio bus and transitions to * D3. Pin widget shuts down and supports presence detect if enabled. Remains in D0 state.
Converter and Pin Widgets are in low power D3 state. Supports presence detect if enabled.
26
DS880F1
CS4207
4.6 Power State Settings Reset (PS-SettingsReset)
PS-SettingsReset is reported as set to one `1'b when, during any low power state transition the settings that were changed from the defaults (either through software or hardware) have been reset back to their default state. When these settings have not been reset, this is reported as `0'b. The conditions that may reset settings to their defaults are: 1. Power On; always sets the PS-SettingsReset to `1'b for all widgets that report EPSS set to `1'b and that have host programmable settings and reset all settings. 2. Double Function Group Reset: sets PS-SettingsReset to `1'b for all widgets that report EPSS set to one (1) and that have host programmable settings and resets all settings. Single Function Group Reset, Link Reset or BITCLK stopped will not cause the PS-SettingsReset bit to be set to `1'b. All settings should persist across these events. The PS-SettingsReset will be reported at the individual widget level and at the Audio Function Group level. The PS-SettingsReset bit for the Audio Function Group is handled differently than at the widget level. For the Audio Function Group the PS-SettingsReset bit is set to `1'b when any widget sets its PS-SettingsReset to `1'b. The Audio Function Group's PS-SettingsReset bit is the logical "or" of all the PS-SettingsReset bits, but is latched so that it can be reset independently and not require all the individual widget PS-SettingsReset bits be reset. This allows a simple poll by the host software to detect when some settings have been reset/changed. For widgets that do not support the EPSS bit, reporting PS-SettingsReset is not required. If the PS-SettingsReset bit is set to `1'b, then this bit for individual widgets, will be cleared to `0'b on receipt of any "Set" verb to that widget; or after responding to a "Get" Power State verb, to that widget.
`1'b D Power On Reset or Double Function Group Reset CLK Q CLR Get "Power State" Verb Q Function Group PS_Settings Reset Bit
Bit settings within converters and pin widgets that software changed from their defaults will not be changed by hardware across any Dx state transition, single function group resets or link resets. Table 1 on page 28 outlines the handling of setting persistence should be performed across Dx states, clock stopping and resets. Because the CS4207 supports EPSS, the use of PS-SettingsReset to report that settings have been reset (changed) is required.
DS880F1
27
CS4207
4.7 Register Settings Across Resets
The CS4207 will perform a complete Power On Reset (POR) initialization if the voltage is cycled from off to on from the VD pin of the device. All registers will be initialized to the default state. For device behavior due to other system reset conditions or power state transitions events, see the table below.
Setting
Action with Link Reset
Action with "Double" Function Group reset
Persist across "Double" FG reset
Action with "Single" Function Group reset
Persist across "Single" FG reset
Action across D0/D3 state transitions or link BITCLK stopped
Persist across Dx state transitions or BITCLK stopped.
Unique codec physical address (SDI)
Requires codec initialization sequence to acquire new unique address. Persist across Link Reset
Converter Format; Type, Base, Mult, Div, Bits Chan fields (verb ID = A00/2xx) Amplifier Gain/Mute (verb ID = Bxx/3xx)
Settings are reset to POR default value. PS-SettingsReset set to `1'b. Settings are reset to POR default value. PS-SettingsReset set to `1'b. Settings are reset to POR default value. PS-SettingsReset set to `1'b. Power State persist across "Double" FG reset
Persist across "Single" FG reset
Persist across Dx state transitions or BITCLK stopped.
Index, Mute and Gain settings persist across Link Reset
Index, Mute and Gain settings persist across "Single" FG reset
Index, Mute and Gain settings persist across Dx state transitions or BITCLK stopped. Persist across Dx state transitions or BITCLK stopped.
Connection Select Control (verb ID = F01/701)
Persist across Link Reset
Persist across "Single" FG reset
Power States for the function group and individual widgets (verb ID = F05/705)
Power State persist across Link Reset
Power State persist across "Single" FG reset
Persist across BITCLK stopped. PS-Act and PS-Set will be updated to the current power state across Dx state transitions. Reset to default across Dx state transitions and does not set PS-SettingsReset to `1'b.
Converter Stream & Channel settings e.g. Stream number and lowest Channel number (verb ID = F06/706) Pin Widget Controls; In/Out Enables, Vref (verb ID = F07/707)
Reset to default by Link reset and does not set PS-SettingsReset to `1'b
Reset to default by "Double" FG reset and does not set PS-SettingsReset to `1'b
Reset to default by "Single" FG reset and does not set PS-SettingsReset to `1'b
Persist across Link Reset
Settings are reset to POR default value. PS-SettingsReset set to `1'b. Settings are reset to POR default value. PS-SettingsReset set to `1'b.
Persist across "Single" FG reset
Persist across Dx state transitions or BITCLK stopped.
Unsolicited Response control; Enable and Tag (verb ID = F08/708)
Persist across Link Reset
Persist across "Single" FG reset
Persist across Dx state transitions or BITCLK stopped.
Table 1. Register Settings Across Reset Conditions 28 DS880F1
CS4207
Pin Sense; Presence Detect Bit only. (verb ID = F09/709)
Update to reflect proper state and save any Unsolicited Response that has not been sent and send it after first verb is received Persist across Link Reset
Update to reflect proper state and issue an Unsolicited Response if enabled.
Update to reflect proper state and issue an Unsolicited Response if enabled.
Update to reflect proper state after transition back to full operation (D0)
EAPD/BTL enable; BTL (verb ID = F0C/70C)
Settings are reset to POR default value. PS-SettingsReset set to `1'b. Settings are reset to POR default value. PS-SettingsReset set to `1'b. Settings are reset to POR default value. PS-SettingsReset set to `1'b.
Persist across "Single" FG reset
Persist across Dx state transitions or BITCLK stopped.
S/PDIF Digital Converter Controls 1 & 2 (verb ID = F0D/70D70E) GPI/GPO Data, Enable Mask, Sticky Masks, Direction (verb ID = F15F1A/715-71A) Configuration Default; all 32 bits (verb ID = F1C/71C71F) Sub-System ID (verb ID = F20/720723) Coefficient Index (verb ID = D/5)
Persist across Link Reset
Persist across "Single" FG reset
Persist across Dx state transitions or BITCLK stopped.
Persist across Link Reset
Persist across "Single" FG reset
Persist across Dx state transitions or BITCLK stopped.
Persist across Link Reset
Persist across "Double" FG reset
Persist across "Single" FG reset
Persist across Dx state transitions or BITCLK stopped.
Persist across Link Reset
Persist across "Double" FG reset
Persist across "Single" FG reset
Persist across Dx state transitions or BITCLK stopped. Persist across Dx state transitions or BITCLK stopped. Persist across Dx state transitions or BITCLK stopped. Persist across Dx state transitions or BITCLK stopped.
Persist across Link Reset
Settings are reset to POR default value.
Persist across "Single" FG reset
Processing Coefficient (verb ID = C/4) Coefficient Registers
Persist across Link Reset
Settings are reset to POR default value.
Persist across "Single" FG reset
Persist across Link Reset
Settings are reset to POR default value. PS-SettingsReset set to `1'b. Digital Loop persists if enabled.
Persist across "Single" FG reset
Digital loop from S/PDIF Receiver pin widget to S/PDIF Transmitter pin widget
Digital Loop persists if enabled.
Digital Loop persists if enabled.
Digital Loop persists if enabled.
Table 1. Register Settings Across Reset Conditions
DS880F1
29
CS4207 5. PRESENCE DETECTION
5.1 Jack Detection Circuit
The jack detection circuit provides attachment for to up to four pluggable jacks as described in the High Definition Audio Specification. Each jack has an isolated switch (normally open), as shown in Figure 7, which closes when a plug is inserted into that jack. A "power of two" parallel resistor network is connected to The SENSE_A pin as shown. The codec will measure the impedance of this network to determine which jacks have plugs inserted and set (or clear) the corresponding "Presence Detect" bit in the "Pin Sense" control for that Pin Widget. The jack detect circuitry will remove switch bounce of up to 250-ms duration.
To Codec To Codec nc Line Out 1 Left & Right
To Codec To Codec nc
Line In Left & Right
To Codec To Codec nc
Mic In Left & Right
To Codec To Codec nc
Headphone Out Left & Right
VA
2.67 k +/- 1%
5.1 k +/- 1%
10.0 k +/- 1%
20.0 k +/- 1%
39.2 k +/- 1%
To Sense_A
Figure 7. Jack Presence Detect Circuit
5.1.1
Presence Detection and Unsolicited Response
The Pin Widget, if enabled to generate an unsolicited response, will deliver one such response for each "de-bounced" state change of the "Presence Detect" bit. The "Presence Detect" bit will be stable and readable at the time an unsolicited response is issued. In sensing the insertion or removal of a jack the codec will measure the impedance continuously to determine when to report a change of state. Reporting of state change and change in the presence detect state bits will not occur until any impedance change has initially stabilized for approximately 250ms. Following this de-bounce period, the codec will report an unsolicited response, if enabled and the HD Audio BITCLK running, within 10ms. If the HD Audio BITCLK is not running, then the request to wake the Link will occur within 10ms. Once an unplug or plug event has been signaled to the host via the unsolicited response, another change of the presence detection bits will not be generated unless the jack state has been sensed (de-bounced) continuously for at least 250ms. Pin Widgets programmed to generate Unsolicited Responses for Presence Detection state changes will continue to function in all power states. When generating an Unsolicited Response for a plug event when the link is in a low power state (when RESET is asserted low) sending of an Unsolicited Response will wait until after the power state change request and initialization request, the codec initialization sequence are complete and the first verb is received to prevent the response from being lost due to software transition to active power state.
30
DS880F1
CS4207
If the codec has detected that the link is entering a Link Reset state (see description below), all Unsolicited Response requests will be buffered. Once the link is in the Link Reset state, with RESET asserted low, the codec will request a power state change and initialization request. Following the codec initialization cycle where a unique address is provided to the CS4207, the codec will then wait for the first verb to be received before issuing the Unsolicited Response to prevent the response from being lost due to software transition to active power state. The Link Reset entry sequence is defined as follows: 1. The HD Audio Bus controller synchronously completes the current frame but does not signal Frame Sync (SYNC) during the last eight SDO bit times. 2. The HD Audio Bus controller synchronously asserts RESET four (or more) BITCLK cycles after the completion of the current frame. 3. BITCLK is stopped a minimum of four clocks, four rising edges, after the assertion of RESET. In the event of a system bus (PCI Bus) reset, the above sequence does not complete, and RESET is asynchronously asserted immediately and unconditionally. When the codec returns to D0 from the D3 lower power state, the state of the presence detection bits will be correct. If the codec power has been removed, the state of the presence detection bits will be reset to the default value and the codec WILL NOT report this by setting the PS-SettingsReset bit for the affected Pin Widget(s). (HDA015-B, March 1,2007 stays that the PS-SettingsReset bit will be set for the affected Pin widget).
5.1.2
S/PDIF Receiver Presence Detect
The presence detect scheme for the S/PDIF Receiver will use the logic state transition of the "LOCK" or "UNLOCK" indicator for the incoming digital stream. The "LOCK" and "UNLOCK" indicators are sticky bits (edge-triggered) which indicate the current state of the receiver. These bits are located in the Vendor Defined Verb at F70, see "S/PDIF RX/TX Interface Status (CIR = 0000h)" on p 128. When the S/PDIF Receiver Input Converter Widget is "enabled" and the "LOCK" indicator is a "1", then the Presence Detect bit in the Pin Sense register will be set to `1'. The S/PDIF IN Converter Widget (NID=07h) and the S/PDIF Receiver pin widget (NID=0Fh) must be in the D0 state to support presence detect using this method described. With an incoming valid S/PDIF signal applied to the SPDIF_IN pin, the "LOCK" status will be valid approximately 200 S/PDIF frames following the receiver being enabled.
DS880F1
31
CS4207 6. HD AUDIO CODEC SUPPORTED VERBS AND RESPONSES
6.1 Software Programming Model
01h GPIO 02h DAC1 PCM; Vol/Mute; D0/D3 Power States 03h DAC2 PCM; Vol/Mute; D0/D3 Power States 04h 11h Processing W idget DAC3 PCM; Vol/Mute; D0/D3 Power States 05h 13h Beep Generator ADC1 PCM; Vol/Mute; D0/D3 Power States 09h Headphone Single-Ended Jack Detect A D0/D3 Power States 0Ah Line Out 1 Balanced Jack Detect D D0/D3 Power States 0Bh Line Out 2 Balanced (Speaker) 0Ch Line In 1/Mic In 2 Boost Jack Detect C D0/D3 Power States 12h Digital Mic In 2 Boost HD_Audio Bus
Jack Sense
06h ADC2 PCM; Vol/Mute; D0/D3 Power States
0Dh Mic In 1/Line In 2 Balanced;Vref;Boost Jack Detect B D0/D3 Power States 0Eh Digital Mic In 1 Boost
07h S/PDIF IN PCM/Non-PCM ; D0/D3 Power States 08h S/PDIF OUT 1 PCM/Non-PCM ; D0/D3 Power States 14h S/PDIF OUT 2 PCM/Non-PCM ; D0/D3 Power States
0Fh S/PDIF Reciever Lock/Unlock Detect D0/D3 Power States 10h S/PDIF Transmitter 1
15h S/PDIF Transmitter 2
Figure 8. Software Programming Model
32
DS880F1
CS4207
6.1.1 Node ID Summary
Node ID Description Reference Section
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h
Root Node Audio Function Group DAC1 Output Converter Widget DAC2 Output Converter Widget DAC3 Output Converter Widget ADC1 Input Converter Widget ADC2 Input Converter Widget S/PDIF Receiver Input Converter Widget S/PDIF Transmitter 1 Output Converter Widget Headphone Pin Widget Line Out 1 Pin Widget Line Out 2 Pin Widget Line In 1/Mic In 2 Pin Widget Mic In 1/Line In 2 Pin Widget Digital Mic 1 In Pin Widget S/PDIF Receiver Input Pin Widget S/PDIF Transmitter 1 Output Pin Widget Processing Widget Digital Mic 2 In Pin Widget Beep Generator Widget S/PDIF Transmitter 2 Output Converter Widget S/PDIF Transmitter 2 Output Pin Widget
Section 6.2 on page 35 Section 6.3 on page 36 Section 6.4 on page 44 Section 6.4 on page 44 Section 6.4 on page 44 Section 6.5 on page 52 Section 6.5 on page 52 Section 6.6 on page 62 Section 6.7 on page 69 Section 6.8 on page 77 Section 6.9 on page 84 Section 6.10 on page 91 Section 6.11 on page 96 Section 6.11 on page 96 Section 6.12 on page 107 Section 6.13 on page 113 Section 6.14 on page 119 Section 6.15 on page 125 Section 6.12 on page 107 Section 6.16 on page 135 Section 6.7 on page 69 Section 6.14 on page 119
Table 2. Device Node ID Summary
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33
CS4207
6.1.2 Pin Configuration Register Defaults
The Configuration Default Register is required for each Pin Widget. It is used by software as an aid in determining the configuration of jacks and devices attached to the codec. At the time the codec is first powered on, this register is internally loaded with default values, see Table 3, indicating the typical system use of this particular pin/jack. After this initial loading, the state, including any software writes into the register, will be preserved across reset events. Its state need not be preserved across power level changes.
Port Location Device Type Color Misc Assoc. Sequence
Headphone Node ID = 09h (see p 83) Line Out 1 Node ID = 0Ah (see p 90) Line Out 2 Node ID = 0Bh (see p 95) Line In 1/Mic In 2 Node ID = 0Ch (see p 103) Mic In 1/Line In 2 Node ID = 0Dh (see p 104) Digital Mic In 1 Node ID = 0Eh (see p 109) S/PDIF In Node ID = 0Fh (see p 118) S/PDIF Out 1 Node ID = 10h (see p 123) Digital Mic In 2 Node ID = 12h (see p 110) S/PDIF Out 2 Node ID = 15h (see p 124)
Jack
External/ Front External/ Rear Internal External/ Rear External/ Rear Internal/ Mobile Lid Inside External/ Front External/ Rear Internal/ Mobile Lid Inside External/ Rear
Headphone
1/8" Jack
Green
No PDC Override
F
0
Jack
Line Outs
1/8" Jack
Green
No PDC Override
F
0
Fixed
Speakers
Other Analog
Unknown
No PDC Override
F
0
Jack
Line In
1/8" Jack
Blue
No PDC Override
5
1
Jack
Mic In
1/8" Jack
Pink
No PDC Override
3
1
Fixed
Digital In
Other Digital
Unknown
No PDC Override
3
E
Jack
S/PDIF In
RCA Jack
White
No PDC Override
F
0
Jack
S/PDIF Out
RCA Jack
Orange
No PDC Override
F
0
Fixed
Digital In
Other Digital
Unknown
No PDC Override
5
E
Jack
S/PDIF Out
Optical
Black
No PDC Override
F
0
Table 3. Pin Configuration Register Defaults
34
DS880F1
CS4207
6.2 6.2.1 Root Node Vendor and Device ID
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 00h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 00h
Response Format:
Bits 31:16 15:0 Type Read Only Read Only Default 1013h 4207h Device ID Description Vendor ID(VID): Cirrus Logic PCI vendor ID
6.2.2
Revision ID
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 00h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 02h
Response Format:
Bits 31:24 23:20 19:16 15:8 Type Read Only Read Only Read Only Read Only Default 00h 1h 0h 03h Reserved Major Revision (MAJREV) of the HDA Spec Minor Revision (MINREV) of the HDA Spec CS4207 Revision ID (REVID) - This indicates the letter rev used for all-layer changes. 01h - rev. A 02h - rev. B 03h - rev. C CS4207 Stepping ID (SID) - This indicates the number rev used for metal layer changes. 00h - rev. A0 or rev. B0 or rev. C0 01h - rev. A1 or rev. C1 Description
7:0
Read Only
01h
6.2.3
Subordinate Node Count
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 00h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 04h
Response Format:
Bits 31:24 23:16 15:8 7:0 Type Read Only Read Only Read Only Read Only Default 00h 01h 00h 01h Reserved Starting Node Number (SNN) Reserved Total Number of Nodes (TNN) Description
DS880F1
35
CS4207
6.3 6.3.1 Audio Function Group (Node ID = 01h) Subordinate Node Count
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 01h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 04h
Response Format:
Bits 31:24 23:16 15:8 7:0 Type Read Only Read Only Read Only Read Only Default 00h 02h 00h 14h Reserved Starting Node Number Reserved Total Number of Nodes equals 20 Description
6.3.2
Function Group Type
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 01h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 05h
Response Format:
Bits 31:9 8 7:0 Type Read Only Read Only Read Only Default 0 0b 01h Reserved Not Unsolicited Capable. This node does not generate an unsolicited response. Node Type - Audio Function Group Description
6.3.3
Audio Function Group Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 01h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 08h
Response Format:
Bits 31:17 16 15:12 Type Read Only Read Only Read Only Default 0 1b 0h Reserved Beep Generation Reserved Input Delay - represents the number of samples between when the sample is received as an analog signal at the pin and when the digital representation is transmitted on the High Definition Audio Link. This may be a "typical" value. Reserved Output Delay - represents the number of samples between when the sample is received from the Link and when it appears as an analog signal at the pin. This may be a "typical" value. Description
11:8
Read Only
9h
7:4 3:0
Read Only Read Only
0h Eh
36
DS880F1
CS4207
6.3.4 Supported PCM Size, Rates
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 01h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Ah
Response Format:
Bits 31:21 20 19 18 17 16 15:12 11 10 9 8 7 6 5 4 3 2 1 0 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 00000000000b 1b 1b 1b 1b 0b 0h 0b 1b 1b 1b 1b 1b 1b 1b 0b 0b 0b 0b Reserved
32-Bit (32B): 32-bit audio format is supported. 24-Bit (24B): 24-bit audio format is supported. 20-Bit (20B): 20-bit audio format is supported. 16-Bit (16B): 16-bit audio format is supported. 8-Bit (8B): 8-bit audio format is not supported.
Description
Reserved
Rate-12 (R12): 384 kHz (48*8) rate is not supported. Rate-11 (R11): 192.0 kHz (48*4) rate is supported. Rate-10 (R10): 176.4 kHz (44.1*4) rate is supported. Rate-9 (R9): 96.0 kHz (48*2) rate is supported. Rate-8 (R8): 88.2 kHz (44.1*2) rate is supported. Rate-7 (R7): 48.0 kHz rate is supported. Rate-6 (R6): 44.1 kHz rate is supported. Rate-5 (R5): 32.0 kHz (48*2/3) rate is supported. Rate-4 (R4): 22.05 kHz (44.1/2) rate is not supported. Rate-3 (R3): 16.0 kHz (48/3) rate is not supported Rate-2 (R2): 11.025 kHz (44.1/4) rate is not supported. Rate-1 (R1): 8.0 kHz (48/6) rate is not supported.
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CS4207
6.3.5 Supported Stream Formats
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 01h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Bh
Response Format:
Bits 31:3 2 1 0 Type Read Only Read Only Read Only Read Only Default 0 0b 0b 1b Reserved
AC-3(R) (AC3): AC3 is not supported. Float32 (FLT32): Float32 formatted data is not supported on this widget. Pulse Code Modulation (PCM): PCM formatted data is supported on this widget.
Description
6.3.6
Supported Power States
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 01h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Fh
Response Format:
Bits 31 Type Read Only Default 1b Description EPSS Supported. Indicates that the Function
Group supports additional capabilities allowing better low power operation.
30 29:5 4 3 Read Only Read Only Read Only Read Only 1b 000000h 0b 1b CLKSTOP Supported Reserved D4 is not Supported D3 is Supported. Since Extended Power States is also supported then the maximum exit time back to fully functional is 10 milliseconds. This is measured from the response to the Set Power State verb that caused the transition from D3 back to fully operational D0 state. D2 is not Supported D1 is not Supported D0 Supported
2 1 0
Read Only Read Only Read Only
0b 0b 1b
CLKSTOP is defined only at the Function Group only (not at the widget level) and indicates that the Function Group and all widgets under it support D3 operation even when there is no BitCLK present on the Link. The maximum exit time back to fully functional is 10 milliseconds from the time that the clock begins operation and a codec address cycle has been completed. The CLKSTOP capability extends the required functionality for D3 support while the link is operational to include:
* * Reporting of presence detect state changes, if enabled and supported by the pin widget, even if the Link Clock is not running (controller low power state) or is currently in a Link Reset condition. Presence state changes occurring during Link Reset will be deferred until after the reset sequence has completed. Presence state change Unsolicited Responses, if enabled, will not be lost because the Link
38
DS880F1
CS4207
Clock stops or if Link Resets are generated before the Unsolicited Response for the state change has been returned to the host. * Reporting of ClkStopOk when stopping of the clock would be permitted. The CLKSTOP is a static capability with ClkStopOk a dynamic reporting. The setting the capability CLKSTOP to one (1) and not allowing the clock to stop by not reporting ClkStopOk is not permissible. Unless there is a condition or dependency that the host software cannot be made aware of, that would prohibit stopping the clock, the ClkStopOk shall be reported as set (1). It is expected that host software will poll the ClkStopOk before stopping the clock if the CLKSTOP is reported at one (1).
6.3.7
GPIO Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 01h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 11h
Response Format:
Bits 31 30 29:24 23:16 15:8 7:0 Type Read Only Read Only Read Only Read Only Read Only Read Only Default 0b 0b 0h 0h 0h 4h Description
GPIOWake; Does not support GPIO wake function. GPIOUnsol; Does not support Unsolicited Response capability.
Reserved
NumGPIs; is an integer representing the number of GPI pins supported by the function. NumGPOs; is an integer representing the number of GPOs supported by the function. NumGPIOs; is an integer representing the number of GPIOs supported by the function.
DS880F1
39
CS4207
6.3.8 Power States
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 01h Bits [19:8] Verb ID = F05h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 01h Bits [19:8] Verb ID = 705h Bits [7:0] Parameter ID = 0xh
Response Format:
Bits 31:11 Type Read Only Default 00000h Reserved
Power State Settings Reset (PS-SettingsReset): This bit is set to `1'b when, during any type of reset or low power state transition, the settings that were changed from the defaults, either by software or hardware, have been reset back to their default state. When these settings have not been reset, this is reported as `0'b. This bit is always a `1'b following a POR condition. For
Description
10
Read Only
1b
more information, see "Power State Settings Reset (PS-SettingsReset)" on p 27.
Power State Clock Stop OK (PS-ClkStopOK): This bit is set to a `1'b when the codec is capable of continuing proper operation even when the HD Audio Bus BITCLK has been stopped. This bit is valid for the Audio Function Group node and not the device widgets. Power State Error (PS-Error): This bit is not supported and will always return `0'b when read.
9
Read Only
1b
8
Read Only
0b
The power state requested by software will always be possible following a reasonable time required to execute the power state transition. There are no dependencies unknown to software between nodes that would inhibit transitioning to the requested power state.
Power State Actual (PS-Act): This field indicates the actual power state of the referenced node. The default state is D3. Power State Set (PS-Set): Writes to these bits set the Audio Function Group to the Power State as described below: PSS = '0000'b; D0 - Fully on. PSS = `0001'b; D1 - Not Supported PSS = `0010'b; D2 - Not Supported PSS = `0011'b; D3 - Allows for lowest possible power consumption under software control. See "D3 Lower Power State Support" on page 25 for more information. PSS = `0100'b; D4 - Not Supported
7:4
Read Only
0011b
3:0
Read/Write
0011b
40
DS880F1
CS4207
PS-Set is a Power State field which defines the current power setting of the referenced node. Since this node is an Audio Function Group node, the actual power state is this setting. Setting this field to the D3 state for the Audio Function Group node will force all other nodes with power state control to the D3 state. If the Power State field for this node is set to D0, then the individual power state for each converter will be uniquely controlled via the corresponding node Power State field. PS-Act is a Power State field which indicates the actual power state of the referenced node. Within the Audio Function Group node, this field will always be equal to the PS-Set field (modulo the time required to execute a power state transition). PS-ClkStopOk is reported as a `1'b when the codec is capable of continuing proper operation in the absence of the HD Audio Bus BITCLK. This bit is reported only at the Audio Function Group level and is reserved at the widget level. After accepting a low power state transition request (D3 state) to the Audio Function Group Node, the codec will begin ramping down all the audio converters. During this time, the PS-ClkStopOK bit will be set to `0'b to signify that the bus BITCLK can not be stopped. Once all the converters have been ramped down, the codec will update the PS-Act bits to reflect the actual transition to the D3 state and will then set the PS-ClkStopOk bit to a `1'b to report the ability of the Codec to operate correctly while in the low power state with the BITCLK stopped. While in the low power D3 state, and with the bus BITCLK stopped, the pin widgets of the codec which were enabled to support unsolicited responses will continue to operate.
6.3.9
GPIO Data
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 01h Bits [19:8] Verb ID = F15h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 01h Bits [19:8] Verb ID = 715h Bits [7:0] Parameter ID = 0xh
Response Format:
Bits 31:8 7:4 Type Read Only Read Only Default 000000h 0h Reserved
GPIO[7:4] Data: Not Supported. GPIO[3:0] Data: For GPIO programmed as inputs, this value is read only and is the sensed value on the corresponding pin. For GPIO programmed as outputs, the value written is driven onto the corresponding pin. Note that if the corresponding bit in the GPIO Enable Mask control is not set, pins configured as outputs will not drive the associated bit value (as the pin must be in a Hi-Z state), but the value returned on a read will still reflect the value that would be driven if the pin were to be enabled in the GPIO Enable Mask control.
Description
3:0
Read/Write
0h
DS880F1
41
CS4207
6.3.10 GPIO Enable Mask
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 01h Bits [19:8] Verb ID = F16h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 01h Bits [19:8] Verb ID = 716h Bits [7:0] Parameter ID = 0xh
Response Format:
Bits 31:8 7:4 Type Read Only Read Only Default 000000h 0h Reserved
GPIO[7:4] Enable Mask: Not Supported. GPIO[3:0] Enable Mask: If the bit associated with a pin is 0, the pin is disabled, and must be in a Hi-Z state. If the bit is a 1, the GPIO pin is enabled and the pin's behavior will be determined by the GPIO Direction control.
Description
3:0
Read/Write
0h
6.3.11
GPIO Direction
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 01h Bits [19:8] Verb ID = F17h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 01h Bits [19:8] Verb ID = 717h Bits [7:0] Parameter ID = 0xh
Response Format:
Bits 31:8 7:4 3:0 Type Read Only Read Only Read/Write Default 000000h 0h 0h Reserved
GPIO[7:4] Direction: Not Supported. GPIO[3:0] Direction: If a bit is a 0, the associated GPIO signal is configured as an input. If the bit is set to a 1, the associated GPIO signal is configured as an output.
Description
6.3.12 GPIO Sticky Mask
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 01h Bits [19:8] Verb ID = F1Ah Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 01h Bits [19:8] Verb ID = 71Ah Bits [7:0] Parameter ID = 0xh
42
DS880F1
CS4207
Response Format:
Bits 31:8 7:4 Type Read Only Read Only Default 000000h 0h Reserved
GPIO[7:4] Sticky Mask: Not Supported. GPIO[3:0] Sticky Mask: Defines GPIO Input Type (0 = Non-Sticky, 1 = Sticky) when a GPIO pin is configured as an input. GPIO inputs configured as Sticky are cleared by writing a 0 to the corresponding bit of the GPIO Data Control The default value for these bits (0h) is all pins Non-Sticky. Non implemented GPIO pins always return 0's. Sticky is defined as Positive-Edge sensitive, Non-Sticky as Level sensitive.
Description
3:0
Read/Write
0h
6.3.13 Subsystem ID
This field provides the subsystem ID and assembly ID of the functional group to software. It is a Read-Write-Once register; BIOS writes to this field to configure the Subsystem ID and Assembly ID during the boot process.
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 01h Bits [19:8] Verb ID = F20h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X CAd = X CAd = X CAd = X Bits [27:20] Node ID = 01h Node ID = 01h Node ID = 01h Node ID = 01h Bits [19:8] Verb ID = 723h Verb ID = 722h Verb ID = 721h Verb ID = 720h Bits [7:0] Parameter ID = xxh SSID[23:16] Parameter ID = xxh SSID[15:8] Parameter ID = xxh SSID[7:0] Parameter ID = xxh Assembly ID[7:0]
Response Format:
Bits 31:24 23:16 15:8 7:0 Type Read/Write Once Read/Write Once Read/Write Once Read/Write Once Default 10h 13h 42h 07h Description Subsystem ID[23:16] Subsystem ID[15:8] Subsystem ID[7:0] Assembly ID[7:0]
6.3.14 Function Reset
Function Reset is an "Execute" verb. There is no physical register associated with the Function Reset. See "Function Group Reset" section on page 24 for more details. Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 01h Bits [19:8] Verb ID = 7FFh Bits [7:0] Parameter ID = 00h
DS880F1
43
CS4207
6.4 6.4.1 DAC1, DAC2, DAC3 Output Converter Widgets (Node ID = 02h, 03h, 04h) Audio Widget Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] DAC1 Node ID=02h DAC2 Node ID=03h DAC3 Node ID=04h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 09h
Response Format:
Bits 31:24 23:20 19:16 15:12 11 10 9 8 7 6 5 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 00h 0h Dh 0h 0b 1b 0b 0b 0b 0b 0b Reserved
Type (TYP): Audio Output Converter Widget Delay (DLY): Number of sample delays through the widget.
Description
Reserved
L-R Swap (LRS): This widget is not capable of swapping the left and right channels. Power Control (PC): Power State control is supported on this widget. Digital (DIG): Widget is not a digital widget. Connection List (CL): A connection list is not present on this widget. Unsolicited Capable (UC): Unsolicited Response is not supported on this widget. Processing Widget (PW): This widget does not contain "Processing Controls" parameters. Stripe (STRP): Stripping is not supported. Format Override (FO): This bit is a `1' to indicate that the widget contains format information, and the "Supported Formats" and "Supported PCM Bits, Rates" should be queried for the widget's format capabilities. Amplifier Parameter Override (APO): This widget contains its own amplifier parameters. Output Amplifier Present (OAP): Output amplifier is present for this widget. Input Amplifier Present (IAP): Input amplifier is not present for this widget. Stereo (ST): A 1 indicates a stereo widget.
4
Read Only
1b
3 2 1 0
Read Only Read Only Read Only Read Only
1b 1b 0b 1b
44
DS880F1
CS4207
6.4.2 Supported PCM Size, Rates
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] DAC1 Node ID=02h DAC2 Node ID=03h DAC3 Node ID=04h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Ah
Response Format:
Bits 31:21 20 19 18 17 16 15:12 11 10 9 8 7 6 5 4 3 2 1 0 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 00000000000b 1b 1b 1b 1b 0b 0h 0b 1b 1b 1b 1b 1b 1b 1b 0b 0b 0b 0b Reserved
32-Bit (32B): 32-bit audio format is supported. 24-Bit (24B): 24-bit audio format is supported. 20-Bit (20B): 20-bit audio format is supported. 16-Bit (16B): 16-bit audio format is supported. 8-Bit (8B): 8-bit audio format is not supported.
Description
Reserved
Rate-12 (R12): 384 kHz (48*8) rate is not supported. Rate-11 (R11): 192.0 kHz (48*4) rate is supported. Rate-10 (R10): 176.4 kHz (44.1*4) rate is supported. Rate-9 (R9): 96.0 kHz (48*2) rate is supported. Rate-8 (R8): 88.2 kHz (44.1*2) rate is supported. Rate-7 (R7): 48.0 kHz rate is supported. Rate-6 (R6): 44.1 kHz rate is supported. Rate-5 (R5): 32.0 kHz (48*2/3) rate is supported. Rate-4 (R4): 22.05 kHz (44.1/2) rate is not supported. Rate-3 (R3): 16.0 kHz (48/3) rate is not supported Rate-2 (R2): 11.025 kHz (44.1/4) rate is not supported. Rate-1 (R1): 8.0 kHz (48/6) rate is not supported.
6.4.3
Supported Stream Formats
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] DAC1 Node ID=02h DAC2 Node ID=03h DAC3 Node ID=04h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Bh
Response Format:
Bits 31:3 2 Type Read Only Read Only Default 0 0b Reserved
AC-3 (AC3): AC3 is not supported.
Description
DS880F1
45
CS4207
1 0 Read Only Read Only 0b 1b
Float32 (FLT32): Float32 formatted data is not supported on this widget. Pulse Code Modulation (PCM): PCM formatted data is supported on this widget.
6.4.4
Supported Power States
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] DAC1 Node ID=02h DAC2 Node ID=03h DAC3 Node ID=04h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Fh
Response Format:
Bits 31 Type Read Only Default 1b Description EPSS Supported. Indicates that the converter
supports additional capabilities allowing better low power operation.
30 29:5 4 3 2 1 0 Read Only Read Only Read Only Read Only Read Only Read Only Read Only 0b 000000h 0b 1b 0b 0b 1b Reserved Reserved D4 is not Supported D3 is Supported. See "D3 Lower Power State Support" on page 25 for more information. D2 is not Supported D1 is not Supported D0 Supported
6.4.5
Output Amplifier Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] DAC1 Node ID=02h DAC2 Node ID=03h DAC3 Node ID=04h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 12h
Response Format:
Bits 31 30:23 22:16 15 14:8 7 6:0 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 1b 00000000b 0000001b 0b 1111111b 0b 1110011b Reserved
Step Size (SS): Indicates that the size of each amplifier's step gain is 0.5dB
Description
Mute Capable (MC): This widget supports mute.
Reserved
Number of Steps (NOS): Indicates there are 128 gain steps; Attenuation range is from +6dB to -57.5dB in 0.5dB steps.
Reserved
Offset (OFST): Indicates that if "1110011b" is programmed into the Amplified Gain Control, it would result in a gain of 0dB.
46
DS880F1
CS4207
6.4.6 Power States
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] DAC1 Node ID=02h DAC2 Node ID=03h DAC3 Node ID=04h Bits [19:8] Verb ID = F05h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] DAC1 Node ID=02h DAC2 Node ID=03h DAC3 Node ID=04h Bits [19:8] Verb ID = 705h Bits [7:0] Parameter ID = 0xh
Response Format:
Bits 31:11 Type Read Only Default 00000h Reserved
Power State Settings Reset(PS-SettingsReset): This bit is set to `1'b when, during any type of reset or low power state transition, the settings within this widget that were changed from the defaults, either by software or hardware, have been reset back to their default state. When these settings have not been reset, this is reported as `0'b. This bit is always a `1'b following a POR condition. For more information,
Description
10
Read Only
1b
see "Power State Settings Reset (PS-SettingsReset)" on p 27
9 8 7:4 Read Only Read Only Read Only 0b 0b 0011b
Power State Clock Stop OK(PS-ClkStopOK): This bit is not supported and will always return `0'b when read. Power State Error (PS-Error): This bit is not supported and will always return `0'b when read. Power State Actual (PS-Act): This field indicates the actual power state of the referenced node. The default state is D3. Power State Set (PS-Set): Writes to these bits set the Audio Function Group to the Power State as described below: PSS = '0000'b; D0 - Fully on. PSS = `0001'b; D1 - Not Supported PSS = `0010'b; D2 - Not Supported PSS = `0011'b; D3 - Allows for lowest possible power consumption under software control. See "D3 Lower Power State Support" on page 25 for more information. PSS = `0100'b; D4 - Not Supported
3:0
Read/Write
0011b
PS-Set is a PowerState field which defines the current power setting of the referenced node. Since this node is of type other than an Audio Function Group node, the actual power state is a function of both this setting and the PowerState setting of the Audio Function Group node under which this node was enumerated (is controlled).
DS880F1
47
CS4207
PS-Act is a PowerState field which indicates the actual power state of this node. Within the Audio Function Group node, this field will always be equal to the PS-Set field (modulo the time required to execute a power state transition). Within this type of node, this field will be the lower power consuming state of either a) the PS-Set field of the currently referenced node or b) the PS-Set field of the Audio Function Group node under which the currently referenced node was enumerated (is controlled).
6.4.7
Converter Stream, Channel
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] DAC1 Node ID=02h DAC2 Node ID=03h DAC3 Node ID=04h Bits [19:8] Verb ID = F06h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] DAC1 Node ID=02h DAC2 Node ID=03h DAC3 Node ID=04h Bits [19:8] Verb ID = 706h Bits [7:0] Parameter ID = xxh
Response Format:
Bits 31:8 Type Read Only Default 000000h Reserved
Stream Number (SN): This field is written by software to indicate the stream number used by the Output Converter. "0h" is stream 0, "1h" is stream 1, etc. By convention, stream 0 is reserved and unused so that converter whose stream number has been reset to "0h" does not unintentionally decode data not intended for them. Lowest Channel Number (LCN): This field is written by software to indicate the lowest channel used by the Output Converter. The stereo converter will use this LCN value plus 1 for its left and right channel.
Description
7:4
Read/Write
0h
3:0
Read/Write
0h
6.4.8
Converter Format
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] DAC1 Node ID=02h DAC2 Node ID=03h DAC3 Node ID=04h Bits [19:8] Verb ID = A00h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] DAC1 Node ID=02h DAC2 Node ID=03h DAC3 Node ID=04h Bits [19:8] Verb ID = 2xxh Bits [7:0] Parameter ID = xxh
Response Format:
48
DS880F1
CS4207
Bits [15:0] must be programmed with the same value programmed into the Stream Descriptor, so that the data format being transmitted on the link matches what is expected by the consumer of the data. If the TYPE is set to Non-PCM, the controller pushes data over the link and is not concerned with formatting. The base rate, data type, and number of Words (MULT) to send each valid frame are specified to control the rate at which the non-PCM data is sent.
Bits 31:16
Type Read Only
Default 0000h Reserved
Description
Stream Type (TYPE): If TYPE is non-zero, the other bits in the format structure have other meanings. 0: PCM 1: Non-PCM
15
Read/Write
0b
14
Read/Write
0b
Sample Base Rate (BASE): 0 = 48 kHz 1 = 44.1 kHz Sample Base Rate Multiple (MULT): 000 = 48 kHz/44.1 kHz or less 001 = x2 (96 kHz, 88.2 kHz, 32 kHz) 010 = x3 (144 kHz) 011 = x4 (192 kHz, 176.4 kHz) 100-111 = Reserved Sample Base Rate Divisor (DIV): 000 = Divide by 1 (48 kHz, 44.1 kHz) 001 = Divide by 2 (24 kHz, 22.05 kHz) 010 = Divide by 3 (16 kHz, 32 kHz) 011 = Divide by 4 (11.025 kHz) 100 = Divide by 5 (9.6 kHz) 101 = Divide by 6 (8 kHz) 110 = Divide by 7 111 = Divide by 8 (6 kHz) Reserved
Bits per Sample (BITS): Bits in each sample: 000 = 8 bits. The data will be packed in memory in 8-bit containers on 16-bit boundaries. 001 = 16 bits. The data will be packed in memory in 16-bit containers on 16-bit boundaries. 010 = 20 bits. The data will be packed in memory in 32-bit containers on 32-bit boundaries. 011 = 24 bits. The data will be packed in memory in 32-bit containers on 32-bit boundaries. 100 = 32 bits. The data will be packed in memory in 32-bit containers on 32-bit boundaries. 101-111 = Reserved Number of Channels (CHAN): Number of channels in each frame of the stream: 0000 = 1 0001 = 2 ... 1111 = 16
13:11
Read/Write
000b
10:8
Read/Write
000b
7
Read Only
0b
6:4
Read/Write
000b
3:0
Read/Write
0000b
DS880F1
49
CS4207
6.4.9 Amplifier Gain/Mute
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] DAC1 Node ID=02h DAC2 Node ID=03h DAC3 Node ID=04h Bits [19:8] Verb ID = Bxxh Bits [7:0] Parameter ID = xxh
Bits [19:8] = `Bxxxx', where bits [15:0] are defined below:
Bits [15:0] 15 14 13 12:4 Value 1b 0b xb 000000000b Description
Get Output/Input (GOI): This bit controls whether the request is for the input amplifier or the output amplifier. When `1', the output amplifier is being requested. When `0', the input amplifier is being requested.
`0'b
Get Left/Right (GLR): This bit controls whether the request is for the left channel amplifier or the right channel amplifier. When `1', the left channel amplifier is being requested. When `0', the right channel amplifier is being requested.
Reserved
Index (IDX): This field specifies the input index of the amplifier setting to return if the widget has multiple input amplifiers. It is only applicable if "Get Output/Input" is `0' which indicates input amplifier is being requested. This field has no meaning and ignored since the widget does not have multiple input amplifiers. It should be always `0's.
3:0
0000b
Response Format:
Bits 31:8 Type Read Only Default 000000h Description Always returned "000000h" Amplifier Mute (AM): This bit returns the Mute setting for the amplifier requested. A 1 indicates the amplifier is in the Mute condition. If the amplifier requested does not exist, a `0' will be returned. Default equals Muted. Amplifier Gain (AG): This field returns the Gain setting for the amplifier requested. If the amplifier requested does not exist, all `0's will be returned Default equals 0 dB.
7
Read Only
1b
6:0
Read Only
1110011b
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] DAC1 Node ID=02h DAC2 Node ID=03h DAC3 Node ID=04h Bits [19:8] Verb ID = 3xxh Bits [7:0] Parameter ID = xxh
Bits [19:8] = `3xxxx', where bits [15:0] are defined below:
Bits 15 Type Write Only Default xb Description
Set Output Amplifier (SOA): Determines if the value programmed refers to the output amplifier. Set to a 1 for the value to be accepted.
50
DS880F1
CS4207
14 Write Only 0b
Set Input Amplifier (SIA): Determines if the value programmed refers to the input amplifier. This bit should always be `0' since an input amplifier is not present on this widget. Set Left Amplifier (SLA): Selects the left channel (channel 0). A 1 indicates that the relevant amplifier should accept the value being set. If both bits are set, both amplifiers are set. Set Right Amplifier (SRA): Selects the right channel (channel 1). A 1 indicates that the relevant amplifier should accept the value being set. If both bits are set, both amplifiers are set. Index (IDX): This field is used when programming the input amplifiers on Selector Widgets and Sum Widgets. This field is ignored. Mute (MUTE): When `1', the Mute is active. When `0', the Mute is inactive. Gain (GAIN): Specifies the amplifier gain in dB.
13
Write Only
xb
12
Write Only
xb
11:8 7 6:0
Write Only Write Only Write Only
0000b xb xxxxxxxb
DS880F1
51
CS4207
6.5 6.5.1 ADC1, ADC2 Input Converter Widgets (Node ID = 05h, 06h) Audio Widget Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] ADC1 Node ID=05h ADC2 Node ID=06h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 09h
Response Format:
Bits 31:24 23:20 19:16 15:12 11 10 9 8 7 6 5 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 00h 1h 8h 0h 0b 1b 0b 1b 0b 0b 0b Reserved
Type (TYP): Audio Input Converter Widget Delay (DLY): Number of sample delays through the widget.
Description
Reserved
L-R Swap (LRS): This widget is not capable of swapping the left and right channels. Power Control (PC): Power State control is supported on this widget. Digital (DIG): Widget is not a digital widget. Connection List (CL): A connection list is present on this widget. Unsolicited Capable (UC): Unsolicited Response is not supported on this widget. Processing Widget (PW): This widget does not contain "Processing Controls" parameters. Stripe (STRP): Stripping is not supported. Format Override (FO): This bit is a `1' to indicate that the widget contains format information, and the "Supported Formats" and "Supported PCM Bits, Rates" should be queried for the widget's format capabilities. Amplifier Parameter Override (APO): This widget contains its own amplifier parameters. Output Amplifier Present (OAP): Is `0' as it is irrelevant to this Audio Input Converter widget. Input Amplifier Present (IAP): Input amplifier is present for this widget. Stereo (ST): A 1 indicates a stereo widget.
4
Read Only
1b
3 2 1 0
Read Only Read Only Read Only Read Only
1b 0b 1b 1b
52
DS880F1
CS4207
6.5.2 Supported PCM Size, Rates
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] ADC1 Node ID=05h ADC2 Node ID=06h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Ah
Response Format:
Bits 31:21 20 19 18 17 16 15:12 11 10 9 8 7 6 5 4 3 2 1 0 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 00000000000b 1b 1b 1b 1b 0b 0h 0b 0b 0b 1b 1b 1b 1b 1b 0b 1b 0b 1b Reserved
32-Bit (32B): 32-bit audio format is supported. 24-Bit (24B): 24-bit audio format is supported. 20-Bit (20B): 20-bit audio format is supported. 16-Bit (16B): 16-bit audio format is supported. 8-Bit (8B): 8-bit audio format is not supported.
Description
Reserved
Rate-12 (R12): 384 kHz (48*8) rate is not supported. Rate-11 (R11): 192.0 kHz (48*4) rate is not supported. Rate-10 (R10): 176.4 kHz (44.1*4) rate is not supported. Rate-9 (R9): 96.0 kHz (48*2) rate is supported. Rate-8 (R8): 88.2 kHz (44.1*2) rate is supported. Rate-7 (R7): 48.0 kHz rate is supported. Rate-6 (R6): 44.1 kHz rate is supported. Rate-5 (R5): 32.0 kHz (48*2/3) rate is supported. Rate-4 (R4): 22.05 kHz (44.1/2) rate is not supported. Rate-3 (R3): 16.0 kHz (48/3) rate is supported Rate-2 (R2): 11.025 kHz (44.1/4) rate is not supported. Rate-1 (R1): 8.0 kHz (48/6) rate is supported.
6.5.3
Supported Stream Formats
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] ADC1 Node ID=05h ADC2 Node ID=06h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Bh
Response Format:
Bits 31:3 2 1 0 Type Read Only Read Only Read Only Read Only Default 0 0b 0b 1b Reserved
AC-3 (AC3): AC-3 data is not supported. Float32 (FLT32): Float32 formatted data is not supported on this widget. Pulse Code Modulation (PCM): PCM formatted data is supported on this widget.
Description
DS880F1
53
CS4207
6.5.4 Input Amplifier Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] ADC1 Node ID=05h ADC2 Node ID=06h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Dh
Response Format:
Bits 31 30:23 22:16 15 Type Read Only Read Only Read Only Read Only Default 1b 00000000b 0000011b 0b Reserved
Step Size (SS): Indicates that the size of each amplifier's step gain is 1.0dB
Description
Mute Capable (MC): Supports muting.
Reserved
Number of Steps (NOS): There are 64 gain steps; Gain range is from +12dB to -51dB in 1.0dB steps.
14:8
Read Only
0111111b
If analog input pin widget is selected as input source, then the range of +12dB to -12dB is from analog PGA and the range of -13dB to -51dB is digital volume control. If the digital mic input pin widget is selected as the input source, then the entire gain range from +12dB to -51dB is digital volume control.
7 6:0
Read Only Read Only
0b 0110011b
Reserved
Offset (OFST): Indicates that if "0110011b" is programmed into the Amplified Gain Control, it would result in a gain of 0dB.
6.5.5
Connection List Length
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] ADC1 Node ID=05h ADC2 Node ID=06h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Eh
Response Format:
Bits 31:8 7 6:0 Type Read Only Read Only Read Only Default 000000h 0b 0000010b Reserved
Long Form (LF): Connection list is short form. Connection List Length (CLL): Two hard-wired inputs are possible for this widget.
Description
54
DS880F1
CS4207
6.5.6 Supported Power States
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] ADC1 Node ID=05h ADC2 Node ID=06h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Fh
Response Format:
Bits 31 Type Read Only Default 1b Description EPSS Supported. Indicates that the converter supports additional capabilities allowing better low power operation. Reserved Reserved D4 is not Supported D3 is Supported. Since Extended Power States is also supported then the maximum exit time back to fully functional is 10 milliseconds. This is measured from the response to the Set Power State verb that caused the transition from D3 back to fully operational D0 state. D2 is not Supported D1 is not Supported D0 Supported
30 29:5 4 3
Read Only Read Only Read Only Read Only
0b 000000h 0b 1b
2 1 0
Read Only Read Only Read Only
0b 0b 1b
6.5.7
ADC1 Connection List Entry
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 05h Bits [19:8] Verb ID = F02h Bits [7:0] Parameter ID = N=00h
Response Format:
Bits 31:24 23:16 15:8 Type Read Only Read Only Read Only Default 00h 00h 12h Description
Connection List Entry (N+3): Returns 00h for N=00h-03h or N>03h. Connection List Entry (N+2): Returns 00h for N=00h-03h or N>03h. Connection List Entry (N+1): Returns 12h (Digital Mic In 2) for N=00h-03h. Returns 00h for N>03h. Connection List Entry (N): Returns 0Ch (Line In 1) for N=00h-03h. Returns 00h for N>03h.
7:0
Read Only
0Ch
6.5.8
ADC1 Connection Select Control
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 05h Bits [19:8] Verb ID = F01h Bits [7:0] Parameter ID = 00h
DS880F1
55
CS4207
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 05h Bits [19:8] Verb ID = 701h Bits [7:0] Parameter ID = xxh
Response Format:
Bits 31:8 Type Read Only Default 000000h Description Reserved Connection Index Value: For a Get command, this field specifies the current connection index. The field is written by software to indicate the connection index value to be set. 00h: Line In 1 (NID=0Ch) 01h: Digital Mic In 2 (NID=12h)
7:0
Read/Write
00h
6.5.9
ADC2 Connection List Entry
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 06h Bits [19:8] Verb ID = F02h Bits [7:0] Parameter ID = N=00h
Response Format:
Bits 31:24 23:16 15:8 Type Read Only Read Only Read Only Default 00h 00h 0Eh Description Connection List Entry (N+3): Returns 00h for N=00h-03h or N>03h. Connection List Entry (N+2): Returns 00h for N=00h-03h or N>03h. Connection List Entry (N+1): Returns 0Eh (Digital Mic In 1) for N=00h-03h. Returns 00h for N>03h Connection List Entry (N): Returns 0Dh (Mic In 1) for N=00h-03h. Returns 00h for N>03h.
7:0
Read Only
0Dh
6.5.10 ADC2 Connection Select Control
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 06h Bits [19:8] Verb ID = F01h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 06h Bits [19:8] Verb ID = 701h Bits [7:0] Parameter ID = xxh
Response Format:
Bits 31:8 Type Read Only Default 000000h Description Reserved Connection Index Value: For a Get command, this field specifies the current connection index. The field is written by software to indicate the connection index value to be set. 00h: Mic In 1 (NID=0Dh) 01h: Digital Mic In 1 (NID=0Eh)
7:0
Read/Write
00h
56
DS880F1
CS4207
6.5.11 Power States
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] ADC1 Node ID=05h ADC2 Node ID=06h Bits [19:8] Verb ID = F05h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] ADC1 Node ID=05h ADC2 Node ID=06h Bits [19:8] Verb ID = 705h Bits [7:0] Parameter ID = 0xh
Response Format:
Bits 31:11 Type Read Only Default 00000h Reserved
Power State Settings Reset(PS-SettingsReset): This bit is set to `1'b when, during any type of reset or low power state transition, the settings within this widget that were changed from the defaults, either by software or hardware, have been reset back to their default state. When these settings have not been reset, this is reported as `0'b. This bit is always a `1'b following a POR condition. For more information,
Description
10
Read Only
1b
see "Power State Settings Reset (PS-SettingsReset)" on p 27
9 8 7:4 Read Only Read Only Read Only 0b 0b 0011b
Power State Clock Stop OK(PS-ClkStopOK): This bit is not supported and will always return `0'b when read. Power State Error (PS-Error): This bit is not supported and will always return `0'b when read. Power State Actual (PS-Act): This field indicates the actual power state of the referenced node. The default state is D3. Power State Set (PS-Set): Writes to these bits set the Audio Function Group to the Power State as described below: PSS = '0000'b; D0 - Fully on. PSS = `0001'b; D1 - Not Supported PSS = `0010'b; D2 - Not Supported PSS = `0011'b; D3 - Allows for lowest possible power consumption under software control. See "D3 Lower Power State Support" on page 25 for more information. PSS = `0100'b; D4 - Not Supported
3:0
Read/Write
0011b
PS-Set is a PowerState field which defines the current power setting of the referenced node. Since this node is of type other than an Audio Function Group node, the actual power state is a function of both this setting and the PowerState setting of the Audio Function Group node under which this node was enumerated (is controlled). PS-Act is a PowerState field which indicates the actual power state of this node. Within the Audio Function Group node, this field will always be equal to the PS-Set field (modulo the time required to execute a DS880F1 57
CS4207
power state transition). Within this type of node, this field will be the lower power consuming state of either a) the PS-Set field of the currently referenced node or b) the PS-Set field of the Audio Function Group node under which the currently referenced node was enumerated (is controlled).
6.5.12 Converter Stream, Channel
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] ADC1 Node ID=05h ADC2 Node ID=06h Bits [19:8] Verb ID = F06h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] ADC1 Node ID=05h ADC2 Node ID=06h Bits [19:8] Verb ID = 706h Bits [7:0] Parameter ID = xxh
Response Format:
Bits 31:8 Type Read Only Default 000000h Reserved
Stream Number (SN): This field is written by software to indicate the stream number used by the Input Converter. "0h" is stream 0, "1h" is stream 1, etc. By convention, stream 0 is reserved and unused so that converter whose stream number has been reset to "0h" does not unintentionally decode data not intended for them. Lowest Channel Number (LCN): This field is written by software to indicate the lowest channel used by the Input Converter. The stereo converter will use this LCN value plus 1 for its left and right channel.
Description
7:4
Read/Write
0h
3:0
Read/Write
0h
6.5.13 Converter Format
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] ADC1 Node ID=05h ADC2 Node ID=06h Bits [19:8] Verb ID = A00h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] ADC1 Node ID=05h ADC2 Node ID=06h Bits [19:8] Verb ID = 2xxh Bits [7:0] Parameter ID = xxh
Response Format:
Bits [15:0] must be programmed by software with the same value programmed into the Stream Descriptor, so that the data format being transmitted on the link matches what is expected by the consumer of the data.
58
DS880F1
CS4207
If the TYPE is set to Non-PCM, the controller pushes data over the link and is not concerned with formatting. The base rate, data type, and number of Words (MULT) to send each valid frame are specified to control the rate at which the non-PCM data is sent.
Bits 31:16 Type Read Only Default 0000h Reserved
Stream Type (TYPE): If TYPE is non-zero, the other bits in the format structure have other meanings. 0: PCM 1: Non-PCM
Description
15
Read/Write
0b
14
Read/Write
0b
Sample Base Rate (BASE): 0 = 48 kHz 1 = 44.1 kHz Sample Base Rate Multiple (MULT): 000 = 48 kHz/44.1 kHz or less 001 = x2 (96 kHz, 88.2 kHz, 32 kHz) 010 = x3 (144 kHz) 011 = x4 (192 kHz, 176.4 kHz) 100-111 = Reserved Sample Base Rate Divisor (DIV): 000 = Divide by 1 (48 kHz, 44.1 kHz) 001 = Divide by 2 (24 kHz, 22.05 kHz) 010 = Divide by 3 (16 kHz, 32 kHz) 011 = Divide by 4 (11.025 kHz) 100 = Divide by 5 (9.6 kHz) 101 = Divide by 6 (8 kHz) 110 = Divide by 7 111 = Divide by 8 (6 kHz) Reserved
Bits per Sample (BITS): Number of bits in each sample: 000 = 8 bits. The data will be packed in memory in 8-bit containers on 16-bit boundaries. 001 = 16 bits. The data will be packed in memory in 16-bit containers on 16-bit boundaries. 010 = 20 bits. The data will be packed in memory in 32-bit containers on 32-bit boundaries. 011 = 24 bits. The data will be packed in memory in 32-bit containers on 32-bit boundaries. 100 = 32 bits. The data will be packed in memory in 32-bit containers on 32-bit boundaries. 101-111 = Reserved Number of Channels (CHAN): Number of channels in each frame of the stream: 0000 = 1 0001 = 2 ... 1111 = 16
13:11
Read/Write
000b
10:8
Read/Write
000b
7
Read Only
0b
6:4
Read/Write
000b
3:0
Read/Write
0000b
DS880F1
59
CS4207
6.5.14 Amplifier Gain/Mute
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] ADC1 Node ID=05h ADC2 Node ID=06h Bits [19:8] Verb ID = Bxxh Bits [7:0] Parameter ID = xxh
Bits [19:8] = `Bxxxx', where bits [15:0] are defined below:
Bits [15:0] 15 14 13 12:4 Value 0b 0b xb 000000000b Description
Get Output/Input (GOI): Controls whether the request is for the input amplifier or the output amplifier. When `0', the input amplifier is being requested. When `1', the output amplifier is being requested.
`0'b
Get Left/Right (GLR): This bit controls whether the request is for the left channel amplifier or the right channel amplifier. When `1', the left channel amplifier is being requested. When `0', the right channel amplifier is being requested.
Reserved
Index (IDX): This field specifies the input index of the amplifier setting to return if the widget has multiple input amplifiers. It is only applicable if "Get Output/Input" is `0' which indicates input amplifier is being requested. This field has no meaning and ignored since the widget does not have multiple input amplifiers. It should be always `0's.
3:0
0000b
Response Format:
Bits 31:8 Type Read Only Default 000000h Description Always returned "000000h"
Amplifier Mute (AM): This bit returns the Mute setting for the amplifier requested. A 1 indicates the amplifier is in the Mute condition. If the amplifier requested does not exist, a `0' will be returned. Default equals Muted. Amplifier Gain (AG): This field returns the Gain setting for the amplifier requested. If the amplifier requested does not exist, all `0's will be returned Default equals 0 dB.
7
Read Only
1b
6:0
Read Only
0110011b
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] ADC1 Node ID=05h ADC2 Node ID=06h Bits [19:8] Verb ID = 3xxh Bits [7:0] Parameter ID = xxh
Bits [19:8] = `3xxxx', where bits [15:0] are defined below:
Bits 15 14 Type Write Only Write Only Default 0b xb Description
Set Output Amplifier (SOA): Bit is always `0' since an output amplifier is not present. Set Input Amplifier (SIA): Determines if the value programmed refers to the input amplifier. Set to a 1 for the value to be accepted.
60
DS880F1
CS4207
13 Write Only xb
Set Left Amplifier (SLA): Selects the left channel (channel 0). A 1 indicates that the relevant amplifier should accept the value being set. If both bits are set, both amplifiers are set. Set Right Amplifier (SRA): Selects the right channel (channel 1). A 1 indicates that the relevant amplifier should accept the value being set. If both bits are set, both amplifiers are set. Index (IDX): This field is used when programming the input amplifiers on Selector Widgets and Sum Widgets. This field is ignored. Mute (MUTE): When `1', the Mute is active. When `0', the Mute is inactive. Gain (GAIN): Specifies the amplifier gain in dB.
12
Write Only
xb
11:8 7 6:0
Write Only Write Only Write Only
0000b xb xxxxxxxb
DS880F1
61
CS4207
6.6 6.6.1 S/PDIF Receiver Input Converter Widget (Node ID = 07h) Audio Widget Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 07h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 09h
Response Format:
Bits 31:24 23:20 19:16 15:12 11 10 9 8 7 6 5 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 00h 1h 8h 0h 0b 1b 1b 1b 1b 0b 0b Reserved
Type (TYP): Audio Input Converter Widget Delay (DLY): Number of sample delays through the widget.
Description
Reserved
L-R Swap (LRS): This widget is not capable of swapping the left and right channels. Power Control (PC): Power State control is supported on this widget. Digital (DIG): Widget is a digital widget. Connection List (CL): A connection list is present on this widget. Unsolicited Capable (UC): Unsolicited Response is supported on this widget. Processing Widget (PW): This widget does not contain "Processing Controls" parameters. Stripe (STRP): Stripping is not supported. Format Override (FO): This bit is a `1' to indicate that the widget contains format information, and the "Supported Formats" and "Supported PCM Bits, Rates" should be queried for the widget's format capabilities. Amplifier Parameter Override (APO): This widget does not contain amplifier parameters. Output Amplifier Present (OAP): Output amplifier is not present for this widget. Input Amplifier Present (IAP): Input amplifier is not present for this widget. Stereo (ST): A 1 indicates a stereo widget.
4
Read Only
1b
3 2 1 0
Read Only Read Only Read Only Read Only
0b 0b 0b 1b
62
DS880F1
CS4207
6.6.2 Supported PCM Size, Rates
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 07h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Ah
Response Format:
Bits 31:21 20 19 18 17 16 15:12 11 10 9 8 7 6 5 4 3 2 1 0 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 00000000000b 1b 1b 1b 1b 0b 0h 0b 1b 0b 1b 0b 1b 1b 1b 0b 0b 0b 0b Reserved
32-Bit (32B): 32-bit audio format is supported. 24-Bit (24B): 24-bit audio format is supported. 20-Bit (20B): 20-bit audio format is supported. 16-Bit (16B): 16-bit audio format is supported. 8-Bit (8B): 8-bit audio format is not supported.
Description
Reserved
Rate-12 (R12): 384 kHz (48*8) rate is not supported. Rate-11 (R11):192.0 kHz(48*4)rate is supported. Rate-10 (R10):176.4 kHz(44.1*4)rate is not supported. Rate-9 (R9): 96.0 kHz (48*2) rate is supported. Rate-8 (R8): 88.2 kHz (44.1*2) rate is not supported. Rate-7 (R7): 48.0 kHz rate is supported. Rate-6 (R6): 44.1 kHz rate is supported. Rate-5 (R5): 32.0 kHz (48*2/3) rate is supported. Rate-4 (R4): 22.05 kHz (44.1/2) rate is not supported. Rate-3 (R3): 16.0 kHz (48/3) rate is not supported Rate-2 (R2): 11.025 kHz (44.1/4) rate is not supported. Rate-1 (R1): 8.0 kHz (48/6) rate is not supported.
6.6.3
Supported Stream Formats
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 07h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Bh
Response Format:
Bits 31:3 2 1 0 Type Read Only Read Only Read Only Read Only Default 0 1b 0b 1b Description Reserved AC-3 (AC3): AC-3 data is supported. Float32 (FLT32): Float32 formatted data is not supported on this widget. Pulse Code Modulation (PCM): PCM formatted data is supported on this widget.
DS880F1
63
CS4207
6.6.4 Connection List Length
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 07h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Eh
Response Format:
Bits 31:8 7 6:0 Type Read Only Read Only Read Only Default 000000h 0b 0000001b Reserved
Long Form (LF): Connection list is short form. Connection List Length (CLL): One hard-wired input is possible for this widget.
Description
6.6.5
Supported Power States
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 07h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Fh
Response Format:
Bits 31 Type Read Only Default 1b Description EPSS Supported. Indicates that the converter
supports additional capabilities allowing better low power operation.
30 29:5 4 3 Read Only Read Only Read Only Read Only 0b 000000h 0b 1b Reserved Reserved D4 is not Supported D3 is Supported. Since Extended Power States is also supported then the maximum exit time back to fully functional is 10 milliseconds. This is measured from the response to the Set Power State verb that caused the transition from D3 back to fully operational D0 state. D2 is not Supported D1 is not Supported D0 Supported
2 1 0
Read Only Read Only Read Only
0b 0b 1b
6.6.6
Connection List Entry
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 07h Bits [19:8] Verb ID = F02h Bits [7:0] Parameter ID = N=00h
Response Format:
Bits 31:24 23:16 Type Read Only Read Only Default 00h 00h Description
Connection List Entry (N+3): Returns 00h for N=00h-03h or N>03h. Connection List Entry (N+2): Returns 00h for N=00h-03h or N>03h.
64
DS880F1
CS4207
15:8 7:0 Read Only Read Only 00h 0Fh
Connection List Entry (N+1): Returns 00h for N=00h-03h or N>03h. Connection List Entry (N): Returns 0Fh (S/PDIF RX) for N=00h-03h. Returns 00h for N>03h.
6.6.7
Power States
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 07h Bits [19:8] Verb ID = F05h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 07h Bits [19:8] Verb ID = 705h Bits [7:0] Parameter ID = 0xh
Response Format:
Bits 31:11 Type Read Only Default 00000h Reserved
Power State Settings Reset(PS-SettingsReset): This bit is set to `1'b when, during any type of reset or low power state transition, the settings within this widget that were changed from the defaults, either by software or hardware, have been reset back to their default state. When these settings have not been reset, this is reported as `0'b. This bit is always a `1'b following a POR condition. For more information,
Description
10
Read Only
1b
see "Power State Settings Reset (PS-SettingsReset)" on p 27
9 8 7:4 Read Only Read Only Read Only 0b 0b 0011b
Power State Clock Stop OK(PS-ClkStopOK): This bit is not supported and will always return `0'b when read. Power State Error (PS-Error): This bit is not supported and will always return `0'b when read. Power State Actual (PS-Act): This field indicates the actual power state of the referenced node. The default state is D3. Power State Set (PS-Set): Writes to these bits set the Audio Function Group to the Power State as described below: PSS = '0000'b; D0 - Fully on. PSS = `0001'b; D1 - Not Supported PSS = `0010'b; D2 - Not Supported PSS = `0011'b; D3 - Allows for lowest possible power consumption under software control. See "D3 Lower Power State Support" on page 25 for more information. PSS = `0100'b; D4 - Not Supported
3:0
Read/Write
0011b
PS-Set is a PowerState field which defines the current power setting of the referenced node. Since this node is of type other than an Audio Function Group node, the actual power state is a function of both this DS880F1 65
CS4207
setting and the PowerState setting of the Audio Function Group node under which this node was enumerated (is controlled).
PS-Act is a PowerState field which indicates the actual power state of this node. Within the Audio Function Group node, this field will always be equal to the PS-Set field (modulo the time required to execute a power state transition). Within this type of node, this field will be the lower power consuming state of either a) the PS-Set field of the currently referenced node or b) the PS-Set field of the Audio Function Group node under which the currently referenced node was enumerated (is controlled).
6.6.8
Converter Stream, Channel
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 07h Bits [19:8] Verb ID = F06h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 07h Bits [19:8] Verb ID = 706h Bits [7:0] Parameter ID = xxh
Response Format:
Bits 31:8 Type Read Only Default 000000h Reserved
Stream Number (SN): Indicates the stream number used by the Input Converter. "0h" is stream 0, "1h" is stream 1, etc. By convention, stream 0 is reserved and unused so that converter whose stream number has been reset to "0h" does not unintentionally decode data not intended for them. Lowest Channel Number (LCN): Indicates the lowest channel used by the Input Converter. The stereo converter will use this LCN value plus 1 for its left and right channel.
Description
7:4
Read/Write
0h
3:0
Read/Write
0h
6.6.9
Converter Format
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 07h Bits [19:8] Verb ID = A00h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 07h Bits [19:8] Verb ID = 2xxh Bits [7:0] Parameter ID = xxh
Response Format: Bits [15:0] must be programmed by software with the same value programmed into the Stream Descriptor, so that the data format being transmitted on the link matches what is expected by the consumer of the data. If the TYPE is set to Non-PCM, the controller pushes data over the link and is not concerned with formatting. The base rate, data type, and number of Words (MULT) to send each valid frame are specified to control the rate at which the non-PCM data is sent.
66
DS880F1
CS4207
Bits 31:16 Type Read Only Default 0000h Description Reserved Stream Type (TYPE): If TYPE is non-zero, the other bits in the format structure have other meanings. 0: PCM 1: Non-PCM Sample Base Rate (BASE): 0 = 48 kHz 1 = 44.1 kHz Sample Base Rate Multiple (MULT): 000 = 48 kHz/44.1 kHz or less 001 = x2 (96 kHz, 88.2 kHz, 32 kHz) 010 = x3 (144 kHz) 011 = x4 (192 kHz, 176.4 kHz) 100-111 = Reserved Sample Base Rate Divisor (DIV): 000 = Divide by 1 (48 kHz, 44.1 kHz) 001 = Divide by 2 (24 kHz, 22.05 kHz) 010 = Divide by 3 (16 kHz, 32 kHz) 011 = Divide by 4 (11.025 kHz) 100 = Divide by 5 (9.6 kHz) 101 = Divide by 6 (8 kHz) 110 = Divide by 7 111 = Divide by 8 (6 kHz) Reserved Bits per Sample (BITS): Number of bits in each sample: 000 = 8 bits. The data will be packed in memory in 8-bit containers on 16-bit boundaries. 001 = 16 bits. The data will be packed in memory in 16-bit containers on 16-bit boundaries. 010 = 20 bits. The data will be packed in memory in 32-bit containers on 32-bit boundaries. 011 = 24 bits. The data will be packed in memory in 32-bit containers on 32-bit boundaries. 100 = 32 bits. The data will be packed in memory in 32-bit containers on 32-bit boundaries. 101-111 = Reserved Number of Channels (CHAN): Number of channels in each frame of the stream: 0000 = 1 0001 = 2 ... 1111 = 16
15
Read/Write
0b
14
Read/Write
0b
13:11
Read/Write
000b
10:8
Read/Write
000b
7
Read Only
0b
6:4
Read/Write
000b
3:0
Read/Write
0000b
DS880F1
67
CS4207
6.6.10 Digital Converter Control
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 07h Bits [19:8] Verb ID = F0D/** Bits [7:0] Parameter ID = 00h
** Note: Address F0Eh is not supported. Set Parameter Command Format:
Bits [31:28] CAd = X Response Format: Bits [27:20] Node ID = 07h Bits [19:8] Verb ID =70D Verb ID =70E Bits [7:0] Parameter ID =Bits[7:0] Parameter ID =Bits[15:8]
The S/PDIF IEC Control (SIC) bits are supported in one of two ways. In the first case referred to as "Codec Formatted SPDIF," on an input PCM stream of less than 32 bits, the codec strips off the SIC bits before transferring the samples to the system and puts them in the Digital Converter Control for later software access. In the second case, referred to as "Software Formatted (or Raw) SPDIF," on a 32-bit input stream, the entire stream is transferred into the system without the codec stripping any bits. However, the codec must properly interpret the Sync Preamble bits of the stream and then send the appropriately coded preamble. The IEC60958 specification, Section 4.3, "Preambles," defines the preambles and the coding to be used. Software will specify the "B," "M," or "W" (also known as "X," "Y," or "Z") preambles by encoding the last four bits of the preamble into the Sync Preamble section (bits 0-3) of the frame. The codec must examine the bits specified and encode the proper preamble based on the previous state. The previous state is to be maintained by the codec hardware.
Bits 31:16 15 14:8 7 6 5 4 3 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 0000h 0b 0000000b 0b 0b 0b 1b 1b Reserved Reserved
CC[6:0] (Category Code): Programmed according to IEC standards, or as appropriate. L (Generation Level): Programmed according to IEC standards, or as appropriate. PRO (Professional): 1 indicates Professional use of channel status; 0 indicates Consumer. /AUDIO (Non-Audio): 1 indicates data is nonPCM format; 0 indicates data is PCM. COPY (Copyright): 1 indicates copyright is asserted; 0 indicates copyright is not asserted. PRE (Pre-emphasis): 1 indicates filter preemphasis is 50/15 us; 0 pre-emphasis is none. VCFG (Validity Config.): This bit is only defined for Output Converters and is defined as Reserved, with a Read Only value of 0 for Input Converters. V (Validity): This bit reflects the "Validity flag," transmitted in each subframe. DigEn (Digital Enable): Enables or disables digital transmission. A 1 indicates that the digital data can pass through the node. A 0 indicates that the digital data is blocked from passing through the node, regardless of the state.
Description
2
Read Only
0b
1
Read Only
0b
0
Read/Write
0b
68
DS880F1
CS4207
6.7 S/PDIF Transmitter 1, S/PDIF Transmitter 2 Output Converter Widgets (Node ID = 08h, 14h) Audio Widget Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
S/P Tx 1 Node ID=08h S/P Tx 2 Node ID=14h
6.7.1
Bits [19:8] Verb ID = F00h
Bits [7:0] Parameter ID = 09h
Response Format:
Bits 31:24 23:20 19:16 15:12 11 10 9 8 7 6 5 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 00h 0h 4h 0h 0b 1b 1b 0b 0b 0b 0b Reserved
Type (TYP): Audio Output Converter Widget Delay (DLY): Number of sample delays through the widget.
Description
Reserved
L-R Swap (LRS): This widget is not capable of swapping the left and right channels. Power Control (PC): Power State control is supported on this widget. Digital (DIG): Widget is a digital widget. Connection List (CL): A connection list is not present on this widget. Unsolicited Capable (UC): Unsolicited Response is not supported on this widget. Processing Widget (PW): This widget does not contain "Processing Controls" parameters. Stripe (STRP): Stripping is not supported. Format Override (FO): This bit is a `1' to indicate that the widget contains format information, and the "Supported Formats" and "Supported PCM Bits, Rates" should be queried for the widget's format capabilities. Amplifier Parameter Override (APO): This widget does not contain amplifier parameters. Output Amplifier Present (OAP): Output amplifier is not present for this widget. Input Amplifier Present (IAP): Input amplifier is not present for this widget. Stereo (ST): A 1 indicates a stereo widget.
4
Read Only
1b
3 2 1 0
Read Only Read Only Read Only Read Only
0b 0b 0b 1b
DS880F1
69
CS4207
6.7.2 Supported PCM Size, Rates
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
S/P Tx 1 Node ID=08h S/P Tx 2 Node ID=14h
Bits [19:8] Verb ID = F00h
Bits [7:0] Parameter ID = 0Ah
Response Format:
Bits 31:21 20 19 18 17 16 15:12 11 10 9 8 7 6 5 4 3 2 1 0 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 00000000000b 1b 1b 1b 1b 0b 0h 0b 1b 1b 1b 1b 1b 1b 1b 0b 0b 0b 0b Reserved
32-Bit (32B): 32-bit audio format is supported. 24-Bit (24B): 24-bit audio format is supported. 20-Bit (20B): 20-bit audio format is supported. 16-Bit (16B): 16-bit audio format is supported. 8-Bit (8B): 8-bit audio format is not supported.
Description
Reserved
Rate-12 (R12): 384 kHz (48*8) rate is not supported. Rate-11 (R11):192.0 kHz(48*4) rate is supported. Rate-10 (R10):176.4 kHz(44.1*4) rate is supported. Rate-9 (R9): 96.0 kHz (48*2) rate is supported. Rate-8 (R8): 88.2 kHz (44.1*2) rate is supported. Rate-7 (R7): 48.0 kHz rate is supported. Rate-6 (R6): 44.1 kHz rate is supported. Rate-5 (R5): 32.0 kHz (48*2/3) rate is supported. Rate-4 (R4): 22.05 kHz (44.1/2) rate is not supported. Rate-3 (R3): 16.0 kHz (48/3) rate is not supported Rate-2 (R2): 11.025 kHz (44.1/4) rate is not supported. Rate-1 (R1): 8.0 kHz (48/6) rate is not supported.
6.7.3
Supported Stream Formats
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
S/P Tx 1 Node ID=08h S/P Tx 2 Node ID=14h
Bits [19:8] Verb ID = F00h
Bits [7:0] Parameter ID = 0Bh
Response Format:
Bits 31:3 2 1 Type Read Only Read Only Read Only Default 0 1b 0b Reserved
AC-3 (AC3): AC-3 data is supported. Float32 (FLT32): Float32 formatted data is not supported on this widget.
Description
70
DS880F1
CS4207
0 Read Only 1b
Pulse Code Modulation (PCM): PCM formatted data is supported on this widget.
6.7.4
Supported Power States
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
S/P Tx 1 Node ID=08h S/P Tx 2 Node ID=14h
Bits [19:8] Verb ID = F00h
Bits [7:0] Parameter ID = 0Fh
Response Format:
Bits 31 Type Read Only Default 1b Description EPSS Supported. Indicates that the converter supports additional capabilities allowing better low power operation. Reserved Reserved D4 is not Supported D3 is Supported. Since Extended Power States is also supported then the maximum exit time back to fully functional is 10 milliseconds. This is measured from the response to the Set Power State verb that caused the transition from D3 back to fully operational D0 state. D2 is not Supported D1 is not Supported D0 Supported
30 29:5 4 3
Read Only Read Only Read Only Read Only
0b 000000h 0b 1b
2 1 0
Read Only Read Only Read Only
0b 0b 1b
6.7.5
Power States
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
S/P Tx 1 Node ID=08h S/P Tx 2 Node ID=14h
Bits [19:8] Verb ID = F05h
Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
S/P Tx 1 Node ID=08h S/P Tx 2 Node ID=14h
Bits [19:8] Verb ID = 705h
Bits [7:0] Parameter ID = 0xh
Response Format:
Bits 31:11 Type Read Only Default 00000h Reserved Description
DS880F1
71
CS4207
Power State Settings Reset(PS-SettingsReset): This bit is set to `1'b when, during any type of reset or low power state transition, the settings within this widget that were changed from the defaults, either by software or hardware, have been reset back to their default state. When these settings have not been reset, this is reported as `0'b. This bit is always a `1'b following a POR condition. For more information,
10
Read Only
1b
see "Power State Settings Reset (PS-SettingsReset)" on p 27
9 8 7:4 Read Only Read Only Read Only 0b 0b 0011b
Power State Clock Stop OK(PS-ClkStopOK): This bit is not supported and will always return `0'b when read. Power State Error (PS-Error): This bit is not supported and will always return `0'b when read. Power State Actual (PS-Act): This field indicates the actual power state of the referenced node. The default state is D3. Power State Set (PS-Set): Writes to these bits set the Audio Function Group to the Power State as described below: PSS = '0000'b; D0 - Fully on. PSS = `0001'b; D1 - Not Supported PSS = `0010'b; D2 - Not Supported PSS = `0011'b; D3 - Allows for lowest possible power consumption under software control. See "D3 Lower Power State Support" on page 25 for more information. PSS = `0100'b; D4 - Not Supported
3:0
Read/Write
0011b
PS-Set is a PowerState field which defines the current power setting of the referenced node. Since this node is of type other than an Audio Function Group node, the actual power state is a function of both this setting and the PowerState setting of the Audio Function Group node under which this node was enumerated (is controlled). PS-Act is a PowerState field which indicates the actual power state of this node. Within the Audio Function Group node, this field will always be equal to the PS-Set field (modulo the time required to execute a power state transition). Within this type of node, this field will be the lower power consuming state of either a) the PS-Set field of the currently referenced node or b) the PS-Set field of the Audio Function Group node under which the currently referenced node was enumerated (is controlled).
6.7.6
Converter Stream, Channel
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
S/P Tx 1 Node ID=08h S/P Tx 2 Node ID=14h
Bits [19:8] Verb ID = F06h
Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
S/P Tx 1 Node ID=08h S/P Tx 2 Node ID=14h
Bits [19:8] Verb ID = 706h
Bits [7:0] Parameter ID = xxh
72
DS880F1
CS4207
Response Format:
Bits 31:8 Type Read Only Default 000000h Description Reserved Stream Number (SN): Indicates the stream number used by the Output Converter. "0h" is stream 0, "1h" is stream 1, etc. By convention, stream 0 is reserved and unused so that converter whose stream number has been reset to "0h" does not unintentionally decode data not intended for them. Lowest Channel Number (LCN): Indicates the lowest channel used by the Output Converter. The stereo converter will use this LCN value plus 1 for its left and right channel.
7:4
Read/Write
0h
3:0
Read/Write
0h
6.7.7
Converter Format
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
S/P Tx 1 Node ID=08h S/P Tx 2 Node ID=14h
Bits [19:8] Verb ID = A00h
Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
S/P Tx 1 Node ID=08h S/P Tx 2 Node ID=14h
Bits [19:8] Verb ID = 2xxh
Bits [7:0] Parameter ID = xxh
Response Format: Bits [15:0] must be programmed by software with the same value programmed into the Stream Descriptor, so that the data format being transmitted on the link matches what is expected by the consumer of the data. If the TYPE is set to Non-PCM, the controller pushes data over the link and is not concerned with formatting. The base rate, data type, and number of Words (MULT) to send each valid frame are specified to control the rate at which the non-PCM data is sent.
Bits 31:16
Type Read Only
Default 0000h Reserved
Description
Stream Type (TYPE): If TYPE is non-zero, the other bits in the format structure have other meanings. 0: PCM 1: Non-PCM Sample Base Rate (BASE): 0 = 48 kHz 1 = 44.1 kHz Sample Base Rate Multiple (MULT): 000 = 48 kHz/44.1 kHz or less 001 = x2 (96 kHz, 88.2 kHz, 32 kHz) 010 = x3 (144 kHz) 011 = x4 (192 kHz, 176.4 kHz) 100-111 = Reserved
15
Read/Write
0b
14
Read/Write
0b
13:11
Read/Write
000b
DS880F1
73
CS4207
Sample Base Rate Divisor (DIV): 000 = Divide by 1 (48 kHz, 44.1 kHz) 001 = Divide by 2 (24 kHz, 22.05 kHz) 010 = Divide by 3 (16 kHz, 32 kHz) 011 = Divide by 4 (11.025 kHz) 100 = Divide by 5 (9.6 kHz) 101 = Divide by 6 (8 kHz) 110 = Divide by 7 111 = Divide by 8 (6 kHz)
10:8
Read/Write
000b
7
Read Only
0b
Reserved
Bits per Sample (BITS): Number of bits in each sample: 000 = 8 bits. The data will be packed in memory in 8-bit containers on 16-bit boundaries. 001 = 16 bits. The data will be packed in memory in 16-bit containers on 16-bit boundaries. 010 = 20 bits. The data will be packed in memory in 32-bit containers on 32-bit boundaries. 011 = 24 bits. The data will be packed in memory in 32-bit containers on 32-bit boundaries. 100 = 32 bits. The data will be packed in memory in 32-bit containers on 32-bit boundaries. 101-111 = Reserved Number of Channels (CHAN): Number of channels in each frame of the stream: 0000 = 1 0001 = 2 ... 1111 = 16
6:4
Read/Write
000b
3:0
Read/Write
0000b
74
DS880F1
CS4207
6.7.8 Digital Converter Control
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
S/P Tx 1 Node ID=08h S/P Tx 2 Node ID=14h
Bits [19:8] Verb ID = F0D/**
Bits [7:0] Parameter ID = 00h
** Note: Address F0Eh is not supported. Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
S/P Tx 1 Node ID=08h S/P Tx 2 Node ID=14h
Bits [19:8] Verb ID =70D Verb ID =70E
Bits [7:0] Parameter ID = Bits[7:0] Parameter ID = Bits[15:8]
Response Format: The S/PDIF IEC Control (SIC) bits are supported in one of two ways. In the first case referred to as "Codec Formatted SPDIF," if a PCM bit stream of less than 32 bits is specified in the Converter Format control, then the S/PDIF Control bits, including the "V," "PRE," "/AUDIO," and other such bits are embedded in the stream by the codec using the values (SIC bits) from the Digital Converter Control. In the second case referred to as "Software Formatted (or Raw) SPDIF," if a 32-bit stream is specified in the Converter Format control, the S/PDIF IEC Control (SIC) bits are assumed to be embedded in the stream by software, and the raw 32-bit stream is transferred on the link with no modification by the codec. However, the codec must properly interpret the Sync Preamble bits of the stream and then send the appropriately coded preamble. The IEC60958 specification, Section 4.3, "Preambles," defines the preambles and the coding to be used. Software will specify the "B," "M," or "W" (also known as "X," "Y," or "Z") preambles by encoding the last four bits of the preamble into the Sync Preamble section (bits 0-3) of the frame. The codec must examine the bits specified and encode the proper preamble based on the previous state. The previous state is to be maintained by the codec hardware.
Bits 31:16 15 14:8 7 6 5 4 3 Type Read Only Read Only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Default 0000h 0b 0000000b 0b 0b 0b 0b 0b Description Reserved Reserved CC[6:0] (Category Code): Programmed according to IEC standards, or as appropriate. L (Generation Level): Programmed according to IEC standards, or as appropriate. PRO (Professional): 1 indicates Professional use of channel status; 0 indicates Consumer. /AUDIO (Non-Audio): 1 indicates data is nonPCM format; 0 indicates data is PCM. COPY (Copyright): 1 indicates copyright is asserted; 0 indicates copyright is not asserted. PRE (Pre-emphasis): 1 indicates filter preemphasis is 50/15 s; 0 pre-emphasis is none.
DS880F1
75
CS4207
VCFG (Validity Config.): Determines S/PDIF transmitter behavior when data is not being transmitted. When asserted, this bit forces the de-assertion of the S/PDIF "Validity" flag, which is bit 28 transmitted in each S/PDIF subframe. This bit is only defined for Output Converters and is defined as Reserved, with a Read Only value of 0 for Input Converters. If "V" = 0 and "VCFG"=0, then for each S/PDIF subframe (Left and Right) bit[28] "Validity" flag reflects whether or not an internal codec error has occurred (specifically whether the S/PDIF interface received and transmitted a valid sample from the High Definition Audio Link). If a valid sample (Left or Right) was received and successfully transmitted, the "Validity" flag should be 0 for that subframe. Otherwise, the "Validity" flag for that subframe should be transmitted as "1." If "V" = 0 and "VCFG" = 1, then for each S/PDIF subframe (Left and Right), bit[28] "Validity" flag reflects whether or not an internal codec transmission error has occurred. Specifically, an internal codec error should result in the "Validity" flag being set to 1. In the case where the S/PDIF transmitter is not receiving a sample or does not receive a valid sample from the High Definition Audio Controller (Left or Right), the S/PDIF transmitter should set the S/PDIF "Validity" flag to 0 and pad each of the S/PDIF "Audio Sample Word" in question with 0's for the subframe in question. If a valid sample (Left or Right) was received and successfully transmitted, the "Validity" flag should be 0 for that subframe. If "V" = 1 and "VCFG" = 0, then each S/PDIF subframe (Left and Right) should have bit[28] "Validity" flag = 1. This tags all S/PDIF subframes as invalid. "V" = 1 and "VCFG" = 1 state is reserved for future use. Default state, coming out of reset, for "V" and "VCFG" should be 0 and 0 respectively. V (Validity): This bit affects the "Validity flag," bit[28] transmitted in each subframe, and enables the S/PDIF transmitter to maintain connection during error or mute conditions. The behavior of the S/PDIF transmitter with respect to this bit depends on the value of the "VCFG" bit. DigEn (Digital Enable): Enables or disables digital transmission. A 1 indicates that the digital data can pass through the node. A 0 indicates that the digital data is blocked from passing through the node, regardless of the state.
2
Read/Write
0b
1
Read/Write
0b
0
Read/Write
0b
76
DS880F1
CS4207
6.8 6.8.1 Headphone Pin Widget (Node ID = 09h) Audio Widget Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 09h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 09h
Response Format:
Bits 31:24 23:20 19:16 15:12 11 10 9 8 7 6 5 4 3 2 1 0 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 00h 4h 1h 0h 0b 1b 0b 1b 1b 0b 0b 0b 0b 0b 0b 1b Reserved
Type (TYP): Pin Complex Widget Delay (DLY): Number of sample delays through the widget.
Description
Reserved
L-R Swap (LRS): This widget is not capable of swapping the left and right channels. Power Control (PC): Power State control is supported on this widget. Digital (DIG): Widget is not a digital widget. Connection List (CL): A connection list is present on this widget. Unsolicited Capable (UC): Unsolicited Response is supported on this widget. Processing Widget (PW): This widget does not contain "Processing Controls" parameters. Stripe (STRP): Stripping is not supported. Format Override (FO): This widget does not contain format information. Amplifier Parameter Override (APO): This widget does not contain amplifier parameters. Output Amplifier Present (OAP): Output amplifier is not present for this widget. Input Amplifier Present (IAP): Input amplifier is not present for this widget. Stereo (ST): A 1 indicates a stereo widget.
6.8.2
Pin Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 09h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Ch
Response Format:
Bits 31:17 16 15:8 Type Read Only Read Only Read Only Default 0 0b 00h Reserved
EAPD Capable (EAPDC): EAPD not supported. VREF Control (VREFC): VREF generation is not supported by this widget.
Description
DS880F1
77
CS4207
7 6 5 4 3 2 1 0 Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only 0h 0b 0b 1b 1b 1b 0b 0b
HDMI Capable (HDMIC): Does not support HDMI. Balanced I/O Pins (BIOP): This widget does not have balanced I/O pins. Input Capable (INC): Is not input capable. Output Capable (OUTC): This bit is `1' to indicate that the widget is output capable. Headphone Drive Capable (HDC): Widget is capable of driving headphones directly. Presence Detect Capable (PDC): A `1' indicates the widget is capable of performing presence detect. Trigger Required (TR): Trigger is not required for an impedance measurement. Impedance Sense Capable (ISC): This bit is `0' to indicate that the widget does not support impedance sense on the attached peripheral.
6.8.3
Connection List Length
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 09h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Eh
Response Format:
Bits 31:8 7 6:0 Type Read Only Read Only Read Only Default 000000h 0b 0000001b Reserved
Long Form (LF): Connection list is short form. Connection List Length (CLL): One hard-wired input for this widget.
Description
6.8.4
Supported Power States
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 09h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Fh
Response Format:
Bits 31 Type Read Only Default 1b Description EPSS Supported. Indicates that this pin wid-
get supports additional capabilities allowing better low power operation.
30 29:5 4 3 Read Only Read Only Read Only Read Only 0b 000000h 0b 1b Reserved Reserved D4 is not Supported D3 is Supported. Since Extended Power States is also supported, the pin widget will maintain the ability to generate an Unsolicited Response (if this function is enabled) while in the D3 state.
78
DS880F1
CS4207
2 1 0 Read Only Read Only Read Only 0b 0b 1b D2 is not Supported D1 is not Supported D0 Supported
6.8.5
Connection List Entry
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 09h Bits [19:8] Verb ID = F02h Bits [7:0] Parameter ID = N=00h
Response Format:
Bits 31:24 23:16 15:8 7:0 Type Read Only Read Only Read Only Read Only Default 00h 00h 00h 02h Description
Connection List Entry (N+3): Returns 00h for N=00h-03h or N>03h. Connection List Entry (N+2): Returns 00h for N=00h-03h or N>03h. Connection List Entry (N+1): Returns 00h for N=00h-03h or N>03h. Connection List Entry (N): Returns 02h (DAC1) for N=00h-03h. Returns 00h for N>03h.
6.8.6
Power States
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 09h Bits [19:8] Verb ID = F05h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 09h Bits [19:8] Verb ID = 705h Bits [7:0] Parameter ID = 0xh
Response Format:
Bits 31:11 Type Read Only Default 00000h Reserved
Power State Settings Reset(PS-SettingsReset): This bit is set to `1'b when, during any type of reset or low power state transition, the settings within this widget that were changed from the defaults, either by software or hardware, have been reset back to their default state. When these settings have not been reset, this is reported as `0'b. This bit is always a `1'b following a POR condition. For more information,
Description
10
Read Only
1b
see "Power State Settings Reset (PS-SettingsReset)" on p 27
9 Read Only 0b
Power State Clock Stop OK(PS-ClkStopOK): This bit is not supported and will always return `0'b when read.
DS880F1
79
CS4207
8 7:4 Read Only Read Only 0b 0011b
Power State Error (PS-Error): This bit is not supported and will always return `0'b when read. Power State Actual (PS-Act): This field indicates the actual power state of the referenced node. The default state is D3. Power State Set (PS-Set): Writes to these bits set the Audio Function Group to the Power State as described below: PSS = '0000'b; D0 - Fully on. PSS = `0001'b; D1 - Not Supported PSS = `0010'b; D2 - Not Supported PSS = `0011'b; D3 - Allows for lowest possible power consumption under software control. See "D3 Lower Power State Support" on page 25 for more information. PSS = `0100'b; D4 - Not Supported
3:0
Read/Write
0011b
PS-Set is a PowerState field which defines the current power setting of the referenced node. Since this node is of type other than an Audio Function Group node, the actual power state is a function of both this setting and the PowerState setting of the Audio Function Group node under which this node was enumerated (is controlled). PS-Act is a PowerState field which indicates the actual power state of this node. Within the Audio Function Group node, this field will always be equal to the PS-Set field (modulo the time required to execute a power state transition). Within this type of node, this field will be the lower power consuming state of either a) the PS-Set field of the currently referenced node or b) the PS-Set field of the Audio Function Group node under which the currently referenced node was enumerated (is controlled).
6.8.7
Pin Widget Control
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 09h Bits [19:8] Verb ID = F07h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Response Format: Bits 31:8 Type Read Only Default 0000h Reserved
H-Phone Enable (HPE): This bit has no affect on the output path. Per HD Audio spec, a `1' enables a low impedance amplifier associated with the output. When `0', this bit disables a low impedance amplifier associated with the output. Output Enable (OUTE): This bit has no affect on the output path. Per HD Audio spec, a `1' enables the output path of the Pin Widget. When `0', the output path of the Pin Widget is shut off. Input Enable (INE): Set to `0' since there is no input path associated with the pin widget.
Bits [27:20] Node ID = 09h
Bits [19:8] Verb ID = 707h
Bits [7:0] Parameter ID = xxh
Description
7
Read/Write
0b
6
Read/Write
0b
5 4:3
Read Only Read Only
0b 00b
Reserved
80
DS880F1
CS4207
VREF Enable (VREFE): This field selects one of the possible states for the VREF signal(s). The Pin Widget does not support VREF generation as indicated in the Pin Capabilities. As such, this field will always be "000b" to select Hi-Z state.
2:0
Read Only
000b
6.8.8
Unsolicited Response Control
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 09h Bits [19:8] Verb ID = F08h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Response Format Bits [27:20] Node ID = 09h Bits [19:8] Verb ID = 708h Bits [7:0] Parameter ID = xxh[
Bits [31:0] are sticky and will not be reset by a Link Reset or a Function Group Reset:
Bits 31:8 7 6 Type Read Only Read/Write Read Only Default 000000h 0b 0b Reserved
Enable: Controls the actual generation of Unsolicited Responses. 1 is enable; 0 is disable.
Description
Reserved
Tag: Is a 6 bit value assigned and used by software to determine what codec node generated the unsolicited response. The value programmed into the Tag field is returned in the top 6 bits (31:26) of every Unsolicited Response generated by this node.
5:0
Read/Write
000000b
Unsolicited Response Format :
Bits [31:26] Tag Bits [27:0] Response
6.8.9
Pin Sense
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 09h Bits [19:8] Verb ID = F09h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Get Response Format: Bits 31 Type Read Only Default 0b Description
Presence Detect (PDET): A `1' indicates that something is plugged into the jack associated with the Pin Widget. A `0' indicates that nothing is plugged in.
Bits [27:20] Node ID = 09h
Bits [19:8] Verb ID = 709h
Bits [7:0] Parameter ID = xxh
DS880F1
81
CS4207
30:0 Read Only 0
Impedance Sense (IMPS): Not valid since the widget is not capable of impedance sensing.
Set Parameter ID [7:0] Format: Bits 7:1 0 Type Write Only Write Only Default 0000000b 0b Reserved
Right Channel (RCHAN): The write to this bit is ignored since the widget is not capable of impedance sensing.
Description
82
DS880F1
CS4207
6.8.10 Configuration Default
The Configuration Default register is used by software as an aid in determining the configuration of jacks and devices attached to the codec. At the time the codec is first powered on, this register is internally loaded with default values indicating the typical system use of this particular pin/jack. After this initial loading, it is completely codec opaque, and its state, including any software writes into the register, must be preserved across reset events such as LINK Reset or Codec Reset (the Function Reset Verb). Its state need not be preserved across power level changes. Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 09h Bits [19:8] Verb ID = F1Ch Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 09h Bits [19:8] Verb ID = 71Ch Verb ID = 71Dh Verb ID = 71Eh Verb ID = 71Fh Bits [7:0] Parameter ID = xxh[7:0] Parameter ID = xxh[15:8] Parameter ID = xxh[23:16] Parameter ID = xxh[31:24]
Response Format
Bits [31:0] are sticky and will not be reset by a Link Reset or a Codec Reset:
Bits 31:30 Type Read/Write Default 00b Description
Port Connectivity (PCON): The external connectivity of this Pin Widget is a jack. Location (LOC): This field indicates the physical location of the jack or device to which the pin complex is connected. Set to External Front Panel. Default Device (DD): Indicates the intended use of the jack is for headphone. Connection Type (CTYP): Indicates the type of physical connection is an 1/8" jack. Color (COL): This field indicates the color of the physical jack for use by software. The color selected is green. Miscellaneous (MISC): No PDC override. Default Association (DA): This field is used by software to group Pin Complex (and therefore jacks) together into functional blocks to support multichannel operation. All jacks with the same association number may be assumed to be grouped together. A value of all `0's is reserved. A value of all `1's in this field indicates that the Association has the lowest priority. Sequence (SEQ): This field indicates the order of the jacks in the association group.
29:24
Read/Write
000010b
23:20 19:16 15:12 11:8
Read/Write Read/Write Read/Write Read/Write
2h 1h 4h 0h
7:4
Read/Write
Fh
3:0
Read/Write
0h
DS880F1
83
CS4207
6.9 6.9.1 Line Out 1 Pin Widget (Node ID = 0Ah) Audio Widget Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Ah Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 09h
Response Format:
Bits 31:24 23:20 19:16 15:12 11 10 9 8 7 6 5 4 3 2 1 0 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 00h 4h 1h 0h 0b 1b 0b 1b 1b 0b 0b 0b 0b 0b 0b 1b Reserved
Type (TYP): Pin Complex Widget Delay (DLY): Number of sample delays through the widget.
Description
Reserved
L-R Swap (LRS): This widget is not capable of swapping the left and right channels. Power Control (PC): Power State control is supported on this widget. Digital (DIG): Widget is not a digital widget. Connection List (CL): A connection list is present on this widget. Unsolicited Capable (UC): Unsolicited Response is supported on this widget. Processing Widget (PW): This widget does not contain "Processing Controls" parameters. Stripe (STRP): Stripping is not supported. Format Override (FO): This widget does not contain format information. Amplifier Parameter Override (APO): This widget does not contain amplifier parameters. Output Amplifier Present (OAP): Output amplifier is not present for this widget. Input Amplifier Present (IAP): Input amplifier is not present for this widget. Stereo (ST): A 1 indicates a stereo widget.
84
DS880F1
CS4207
6.9.2 Pin Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Ah Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Ch
Response Format:
Bits 31:17 16 15:8 7 6 5 4 3 2 1 0 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 0 0b 00h 0h 1b 0b 1b 0b 1b 0b 0b Reserved
EAPD Capable (EAPDC): Indicates the widget does not support the EAPD pin. VREF Control (VREFC): VREF generation is not supported by this widget. HDMI Capable (HDMIC): This widget is not capable of supporting HDMI. Balanced I/O Pins (BIOP): This widget has balanced I/O pins. Input Capable (INC): The widget is not input capable. Output Capable (OUTC): This bit is `1' to indicate that the widget is output capable. Headphone Drive Capable (HDC): Widget is not capable of driving headphones directly. Presence Detect Capable (PDC): This bit is `1' to indicate that the widget is capable of performing presence detect. Trigger Required (TR): Trigger is not required for an impedance measurement. Impedance Sense Capable (ISC): This bit is `0' to indicate that the widget does not support impedance sense on the attached peripheral.
Description
6.9.3
Connection List Length
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Ah Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Eh
Response Format:
Bits 31:8 7 6:0 Type Read Only Read Only Read Only Default 000000h 0b 0000001b Reserved
Long Form (LF): Connection list is short form. Connection List Length (CLL): One hard-wired input for this widget.
Description
DS880F1
85
CS4207
6.9.4 Supported Power States
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Ah Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Fh
Response Format:
Bits 31 Type Read Only Default 1b Description EPSS Supported. Indicates that this pin widget supports additional capabilities allowing better low power operation. Reserved Reserved D4 is not Supported D3 is Supported. Since Extended Power States is also supported, the pin widget will maintain the ability to generate an Unsolicited Response (if this function is enabled) while in the D3 state. D2 is not Supported D1 is not Supported D0 Supported
30 29:5 4 3
Read Only Read Only Read Only Read Only
0b 000000h 0b 1b
2 1 0
Read Only Read Only Read Only
0b 0b 1b
6.9.5
Connection List Entry
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Ah Bits [19:8] Verb ID = F02h Bits [7:0] Parameter ID = N=00h
Response Format:
Bits 31:24 23:16 15:8 7:0 Type Read Only Read Only Read Only Read Only Default 00h 00h 00h 03h Description
Connection List Entry (N+3): Returns 00h for N=00h-03h or N>03h. Connection List Entry (N+2): Returns 00h for N=00h-03h or N>03h. Connection List Entry (N+1): Returns 00h for N=00h-03h or N>03h. Connection List Entry (N): Returns 03h (DAC2) for N=00h-03h. Returns 00h for N>03h.
6.9.6
Power States
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Ah Bits [19:8] Verb ID = F05h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Ah Bits [19:8] Verb ID = 705h Bits [7:0] Parameter ID = 0xh
86
DS880F1
CS4207
Response Format:
Bits 31:11 Type Read Only Default 00000h Reserved
Power State Settings Reset(PS-SettingsReset): This bit is set to `1'b when, during any type of reset or low power state transition, the settings within this widget that were changed from the defaults, either by software or hardware, have been reset back to their default state. When these settings have not been reset, this is reported as `0'b. This bit is always a `1'b following a POR condition. For more information,
Description
10
Read Only
1b
see "Power State Settings Reset (PS-SettingsReset)" on p 27
9 8 7:4 Read Only Read Only Read Only 0b 0b 0011b
Power State Clock Stop OK(PS-ClkStopOK): This bit is not supported and will always return `0'b when read. Power State Error (PS-Error): This bit is not supported and will always return `0'b when read. Power State Actual (PS-Act): This field indicates the actual power state of the referenced node. The default state is D3. Power State Set (PS-Set): Writes to these bits set the Audio Function Group to the Power State as described below: PSS = '0000'b; D0 - Fully on. PSS = `0001'b; D1 - Not Supported PSS = `0010'b; D2 - Not Supported PSS = `0011'b; D3 - Allows for lowest possible power consumption under software control. See "D3 Lower Power State Support" on page 25 for more information. PSS = `0100'b; D4 - Not Supported
3:0
Read/Write
0011b
PS-Set is a PowerState field which defines the current power setting of the referenced node. Since this node is of type other than an Audio Function Group node, the actual power state is a function of both this setting and the PowerState setting of the Audio Function Group node under which this node was enumerated (is controlled). PS-Act is a PowerState field which indicates the actual power state of this node. Within the Audio Function Group node, this field will always be equal to the PS-Set field (modulo the time required to execute a power state transition). Within this type of node, this field will be the lower power consuming state of either a) the PS-Set field of the currently referenced node or b) the PS-Set field of the Audio Function Group node under which the currently referenced node was enumerated (is controlled).
6.9.7
Pin Widget Control
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Ah Bits [19:8] Verb ID = F07h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] Bits [27:20] Bits [19:8] Bits [7:0]
DS880F1
87
CS4207
CAd = X Response Format: Bits 31:8 7 Type Read Only Read Only Default 0000h 0b Reserved
H-Phone Enable (HPE): Set to `0' since there is no low impedance amplifier associated with this pin widget. Output Enable (OUTE): This bit has no affect on the output path. Per HD Audio spec, a `1' enables the output path of the Pin Widget. When `0', the output path of the Pin Widget is shut off. Input Enable (INE): Set to `0' since there is no input path associated with the pin widget.
Node ID = 0Ah
Verb ID = 707h
Parameter ID = xxh
Description
6
Read/Write
0b
5 4:3 2:0
Read Only Read Only Read Only
0b 00b 000b
Reserved
VREF Enable (VREFE): The Pin Widget does not support VREF generation as indicated in the Pin Capabilities. As such, this field should always be "000b" to select the Hi-Z state.
6.9.8
Unsolicited Response Control
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Ah Bits [19:8] Verb ID = F08h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Response Format Bits [27:20] Node ID = 0Ah Bits [19:8] Verb ID = 708h Bits [7:0] Parameter ID = xxh[
Bits [31:0] are sticky and will not be reset by a Link Reset or a Function Group Reset:
Bits 31:8 7 6 Type Read Only Read/Write Read Only Default 000000h 0b 0b Reserved
Enable: Controls the actual generation of Unsolicited Responses. 1 is enable; 0 is disable.
Description
Reserved
Tag: Is a 6 bit value assigned and used by software to determine what codec node generated the unsolicited response. The value programmed into the Tag field is returned in the top 6 bits (31:26) of every Unsolicited Response generated by this node.
5:0
Read/Write
000000b
Unsolicited Response Format :
Bits [31:26] Tag Bits [27:0] Response
88
DS880F1
CS4207
6.9.9 Pin Sense
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Ah Bits [19:8] Verb ID = F09h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Get Response Format: Bits 31 Type Read Only Default 0b Description
Presence Detect (PDET): A `1' indicates that there is "something" plugged into the jack associated with the Pin Widget. A `0' indicates that nothing is plugged in. Impedance Sense (IMPS): Not valid since the widget is not capable of impedance sensing.
Bits [27:20] Node ID = 0Ah
Bits [19:8] Verb ID = 709h
Bits [7:0] Parameter ID = xxh
30:0
Read Only
0
Set Parameter ID [7:0] Format: Bits 7:1 0 Type Write Only Write Only Default 0000000b 0b Reserved
Right Channel (RCHAN): The write to this bit is ignored since the widget is not capable of impedance sensing.
Description
6.9.10 EAPD/BTL Enable
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Ah Bits [19:8] Verb ID = F0Ch Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Get Response Format: Bits 31:3 2 1 Type Read Only Read Only Read Only Default 0 0b 0b Reserved
L-R Swap: Not valid since the widget is not capable of left/right swapping. EAPD: EAPD is not supported by this pin widget. BTL: controls the output configuration of a Pin Widget which has indicated support for balanced I/O (bit 6, Pin Capabilities Parameter). When this bit is 0, the output drivers are configured in normal, single-ended mode; when this bit is 1, they are configured in balanced mode.
Bits [27:20] Node ID = 0Ah
Bits [19:8] Verb ID = 70Ch
Bits [7:0] Parameter ID = xxh
Description
0
Read/Write
0b
DS880F1
89
CS4207
6.9.11 Configuration Default
The Configuration Default register is used by software as an aid in determining the configuration of jacks and devices attached to the codec. At the time the codec is first powered on, this register is internally loaded with default values indicating the typical system use of this particular pin/jack. After this initial loading, it is completely codec opaque, and its state, including any software writes into the register, must be preserved across reset events such as LINK Reset or Codec Reset (the Function Reset Verb). Its state need not be preserved across power level changes. Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Ah Bits [19:8] Verb ID = F1Ch Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Ah Bits [19:8] Verb ID = 71Ch Verb ID = 71Dh Verb ID = 71Eh Verb ID = 71Fh Bits [7:0] Parameter ID = xxh[7:0] Parameter ID = xxh[15:8] Parameter ID = xxh[23:16] Parameter ID = xxh[31:24]
Response Format
Bits [31:0] are sticky and will not be reset by a Link Reset or a Codec Reset:
Bits 31:30 Type Read/Write Default 00b Description
Port Connectivity (PCON): The external connectivity of this Pin Widget is a jack. Location (LOC): This field indicates the physical location of the jack or device to which the pin complex is connected. Set to External Rear Panel. Default Device (DD): Indicates the intended use of the jack is for Line Outs. Connection Type (CTYP): Indicates the type of physical connection is an 1/8" jack. Color (COL): This field indicates the color of the physical jack for use by software. The color selected is green. Miscellaneous (MISC): No PDC override. Default Association (DA): This field is used by software to group Pin Complex (and therefore jacks) together into functional blocks to support multichannel operation. All jacks with the same association number may be assumed to be grouped together. A value of all `0's is reserved. A value of all `1's in this field indicates that the Association has the lowest priority. Sequence (SEQ): This field indicates the order of the jacks in the association group.
29:24
Read/Write
000001b
23:20 19:16 15:12 11:8
Read/Write Read/Write Read/Write Read/Write
0h 1h 4h 0h
7:4
Read/Write
Fh
3:0
Read/Write
0h
90
DS880F1
CS4207
6.10 Line Out 2 Pin Widget (Node ID = 0Bh)
6.10.1 Audio Widget Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Bh Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 09h
Response Format:
Bits 31:24 23:20 19:16 15:12 11 10 9 8 7 6 5 4 3 2 1 0 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 00h 4h 1h 0h 0b 0b 0b 1b 0b 0b 0b 0b 0b 0b 0b 1b Reserved
Type (TYP): Pin Complex Widget Delay (DLY): Number of sample delays through the widget.
Description
Reserved
L-R Swap (LRS): This widget is not capable of swapping the left and right channels. Power Control (PC): Power State control is not supported on this widget. Digital (DIG): Widget is not a digital widget. Connection List (CL): A connection list is present on this widget. Unsolicited Capable (UC): Unsolicited Response is not supported on this widget. Processing Widget (PW): This widget does not contain "Processing Controls" parameters. Stripe (STRP): Stripping is not supported. Format Override (FO): This widget does not contain format information. Amplifier Parameter Override (APO): This widget does not contain amplifier parameters. Output Amplifier Present (OAP): Output amplifier is not present for this widget. Input Amplifier Present (IAP): Input amplifier is not present for this widget. Stereo (ST): A 1 indicates a stereo widget.
DS880F1
91
CS4207
6.10.2 Pin Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Bh Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Ch
Response Format:
Bits 31:17 16 15:8 7 6 5 4 3 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 0 0b 00h 0h 1b 0b 1b 0b Reserved
EAPD Capable (EAPDC): Indicates the widget does support the EAPD pin. VREF Control (VREFC): VREF generation is not supported by this widget. HDMI Capable (HDMIC): This widget is not capable of supporting HDMI. Balanced I/O Pins (BIOP): This widget has balanced I/O pins. Input Capable (INC): The widget is not input capable. Output Capable (OUTC): This bit is `1' to indicate that the widget is output capable. Headphone Drive Capable (HDC): Widget is not capable of driving headphones directly. Presence Detect Capable (PDC): This bit is `0' to indicate that the widget is not capable of performing presence detect to determine whether there is anything plugged in. Trigger Required (TR): Trigger is not required for an impedance measurement. Impedance Sense Capable (ISC): This bit is `0' to indicate that the widget does not support impedance sense on the attached peripheral.
Description
2
Read Only
0b
1 0
Read Only Read Only
0b 0b
6.10.3 Connection List Length
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Bh Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Eh
Response Format:
Bits 31:8 7 6:0 Type Read Only Read Only Read Only Default 000000h 0b 0000001b Reserved
Long Form (LF): Connection list is short form. Connection List Length (CLL): One hard-wired input for this widget.
Description
6.10.4 Connection List Entry
Get Parameter Command Format:
Bits [31:28] Bits [27:20] Bits [19:8] Bits [7:0]
92
DS880F1
CS4207
CAd = X Node ID = 0Bh Verb ID = F02h Parameter ID = N=00h
Response Format:
Bits 31:24 23:16 15:8 7:0 Type Read Only Read Only Read Only Read Only Default 00h 00h 00h 04h Description
Connection List Entry (N+3): Returns 00h for N=00h-03h or N>03h. Connection List Entry (N+2): Returns 00h for N=00h-03h or N>03h. Connection List Entry (N+1): Returns 00h for N=00h-03h or N>03h. Connection List Entry (N): Returns 04h (DAC3) for N=00h-03h. Returns 00h for N>03h.
6.10.5 Pin Widget Control
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Bh Bits [19:8] Verb ID = F07h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Response Format: Bits 31:8 7 Type Read Only Read Only Default 0000h 0b Reserved
H-Phone Enable (HPE): Set to `0' since there is no low impedance amplifier associated with this pin widget. Output Enable (OUTE): This bit has no affect on the output path. Per HD Audio spec, a `1' enables the output path of the Pin Widget. When `0', the output path of the Pin Widget is shut off. Input Enable (INE): Set to `0' since there is no input path associated with the pin widget.
Bits [27:20] Node ID = 0Bh
Bits [19:8] Verb ID = 707h
Bits [7:0] Parameter ID = xxh
Description
6
Read/Write
0b
5 4:3 2:0
Read Only Read Only Read Only
0b 00b 000b
Reserved
VREF Enable (VREFE): The Pin Widget does not support VREF generation as indicated in the Pin Capabilities. As such, this field should always be "000b" to select the Hi-Z state.
DS880F1
93
CS4207
6.10.6 EAPD/BTL Enable
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Bh Bits [19:8] Verb ID = F0Ch Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Get Response Format: Bits 31:3 2 1 Type Read Only Read Only Read Only Default 0 0b 0b Reserved
L-R Swap: Not valid since the widget is not capable of left/right swapping. EAPD: EAPD is not supported by this pin widget. BTL: controls the output configuration of a Pin Widget which has indicated support for balanced I/O (bit 6, Pin Capabilities Parameter). When this bit is 0, the output drivers are configured in normal, single-ended mode; when this bit is 1, they are configured in balanced mode.
Bits [27:20] Node ID = 0Bh
Bits [19:8] Verb ID = 70Ch
Bits [7:0] Parameter ID = xxh
Description
0
Read/Write
0b
94
DS880F1
CS4207
6.10.7 Configuration Default
The Configuration Default register is used by software as an aid in determining the configuration of jacks and devices attached to the codec. At the time the codec is first powered on, this register is internally loaded with default values indicating the typical system use of this particular pin/jack. After this initial loading, it is completely codec opaque, and its state, including any software writes into the register, must be preserved across reset events such as LINK Reset or Codec Reset (the Function Reset Verb). Its state need not be preserved across power level changes. Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Bh Bits [19:8] Verb ID = F1Ch Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Bh Bits [19:8] Verb ID = 71Ch Verb ID = 71Dh Verb ID = 71Eh Verb ID = 71Fh Bits [7:0] Parameter ID = xxh[7:0] Parameter ID = xxh[15:8] Parameter ID = xxh[23:16] Parameter ID = xxh[31:24]
Response Format
Bits [31:0] are sticky and will not be reset by a Link Reset or a Codec Reset:
Bits 31:30 Type Read/Write Default 10b Description
Port Connectivity (PCON): The internal connectivity of this Pin Widget is fixed. Location (LOC): This field indicates the physical location of the jack or device to which the pin complex is connected. Set to internal and not available. Default Device (DD): Indicates the intended use of the connection is for speakers. Connection Type (CTYP): Indicates the type of physical connection is other analog. Color (COL): This field indicates the color of the physical jack for use by software. The color selected is unknown. Miscellaneous (MISC): No PDC override. Default Association (DA): This field is used by software to group Pin Complex (and therefore jacks) together into functional blocks to support multichannel operation. All jacks with the same association number may be assumed to be grouped together. A value of all `0's is reserved. A value of all `1's in this field indicates that the Association has the lowest priority. Sequence (SEQ): This field indicates the order of the jacks in the association group.
29:24
Read/Write
010000b
23:20 19:16 15:12 11:8
Read/Write Read/Write Read/Write Read/Write
1h 7h 0h 0h
7:4
Read/Write
Fh
3:0
Read/Write
0h
DS880F1
95
CS4207
6.11 6.11.1 Line In 1/Mic In 2, Mic In 1/Line In 2 Pin Widgets (Node ID = 0Ch, 0Dh) Audio Widget Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
Line In 1 Node ID=0Ch Mic In 1 Node ID=0Dh
Bits [19:8] Verb ID = F00h
Bits [7:0] Parameter ID = 09h
Response Format:
Bits 31:24 23:20 19:16 15:12 11 10 9 8 7 6 5 4 3 2 1 0 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 00h 4h 1h 0h 0b 1b 0b 0b 1b 0b 0b 0b 1b 0b 1b 1b Reserved
Type (TYP): Pin Complex Widget Delay (DLY): Number of sample delays through the widget.
Description
Reserved
L-R Swap (LRS): This widget is not capable of swapping the left and right channels. Power Control (PC): Power State control is supported on this widget. Digital (DIG): Widget is not a digital widget. Connection List (CL): A connection list is not present on this widget. Unsolicited Capable (UC): Unsolicited Response is supported on this widget. Processing Widget (PW): This widget does not contain "Processing Controls" parameters. Stripe (STRP): Stripping is not supported. Format Override (FO): This widget does not contain format information. Amplifier Parameter Override (APO): This widget contains its own amplifier parameters. Output Amplifier Present (OAP): Output amplifier is not present for this widget. Input Amplifier Present (IAP): Input amplifier is present for this widget. Stereo (ST): A 1 indicates a stereo widget.
96
DS880F1
CS4207
6.11.2 Line In 1/Mic In 2 Pin Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Ch Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Ch
Response Format:
Bits 31:17 16 15:8 7 6 5 4 3 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 0 0b 00h 0h 0b 1b 0b 0b Reserved
EAPD Capable (EAPDC): EAPD not supported. VREF Control (VREFC): VREF generation is not supported by this widget. HDMI Capable (HDMIC): HDMI not supported. Balanced I/O Pins (BIOP): This widget does not have balanced I/O pins. Input Capable (INC): Widget is input capable. Output Capable (OUTC): Widget is not output capable. Headphone Drive Capable (HDC): Widget is not capable of driving headphones directly. Presence Detect Capable (PDC): This bit is `1' to indicate that the widget is capable of performing presence detect to determine whether there is anything plugged in. Trigger Required (TR): Trigger is not required for an impedance measurement. Impedance Sense Capable (ISC): This bit is `0' to indicate that the widget does not support impedance sense on the attached peripheral.
Description
2
Read Only
1b
1 0
Read Only Read Only
0b 0b
6.11.3
Mic In 1/Line In 2 Pin Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Dh Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Ch
Response Format:
Bits 31:17 16 15:8 7 6 5 4 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 0 0b 17h 0h 1b 1b 0b Reserved
EAPD Capable (EAPDC): EAPD not supported. VREF Control (VREFC): VREF generation is supported by this widget. Ground/80%/50%/Hi-Z are supported. 100% is not supported. HDMI Capable (HDMIC): HDMI not supported. Balanced I/O Pins (BIOP): This widget has balanced I/O pins. Input Capable (INC): Widget is input capable. Output Capable (OUTC): Widget is not output capable.
Description
DS880F1
97
CS4207
3 Read Only 0b
Headphone Drive Capable (HDC): Widget is not capable of driving headphones directly. Presence Detect Capable (PDC): This bit is `1' to indicate that the widget is capable of performing presence detect to determine whether there is anything plugged in. Trigger Required (TR): Trigger is not required for an impedance measurement. Impedance Sense Capable (ISC): This bit is `0' to indicate that the widget does not support impedance sense on the attached peripheral.
2
Read Only
1b
1 0
Read Only Read Only
0b 0b
6.11.4
Input Amplifier Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
Line In 1 Node ID=0Ch Mic In 1 Node ID=0Dh
Bits [19:8] Verb ID = F00h
Bits [7:0] Parameter ID = 0Dh
Response Format:
Bits 31 30:23 22:16 15 14:8 7 6:0 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 0b 00000000b 0100111b 0b 0000011b 0b 0000000b Reserved
Step Size (SS): Indicates that the size of each amplifier's step gain is 10dB
Description
Mute Capable (MC): Does not support mute.
Reserved
Number of Steps (NOS): There are 4 gain steps; 0dB, +10dB, +20dB, and +30dB.
Reserved
Offset (OFST): Indicates that if "0000000b" is programmed into the Amplified Gain Control, it would result in a gain of 0dB.
6.11.5
Supported Power States
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
Line In 1 Node ID=0Ch Mic In 1 Node ID=0Dh
Bits [19:8] Verb ID = F00h
Bits [7:0] Parameter ID = 0Fh
Response Format:
Bits 31 Type Read Only Default 1b Description EPSS Supported. Indicates that this pin wid-
get supports additional capabilities allowing better low power operation.
30 29:5 4 Read Only Read Only Read Only 0b 000000h 0b Reserved Reserved D4 is not Supported
98
DS880F1
CS4207
3 Read Only 1b D3 is Supported. Since Extended Power States is also supported, the pin widget will maintain the ability to generate an Unsolicited Response (if this function is enabled) while in the D3 state. D2 is not Supported D1 is not Supported D0 Supported
2 1 0
Read Only Read Only Read Only
0b 0b 1b
6.11.6
Power States
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
Line In 1 Node ID=0Ch Mic In 1 Node ID=0Dh
Bits [19:8] Verb ID = F05h
Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
Line In 1 Node ID=0Ch Mic In 1 Node ID=0Dh
Bits [19:8] Verb ID = 705h
Bits [7:0] Parameter ID = 0xh
Response Format:
Bits 31:11 Type Read Only Default 00000h Reserved
Power State Settings Reset(PS-SettingsReset): This bit is set to `1'b when, during any type of reset or low power state transition, the settings within this widget that were changed from the defaults, either by software or hardware, have been reset back to their default state. When these settings have not been reset, this is reported as `0'b. This bit is always a `1'b following a POR condition. For more information,
Description
10
Read Only
1b
see "Power State Settings Reset (PS-SettingsReset)" on p 27
9 8 7:4 Read Only Read Only Read Only 0b 0b 0011b
Power State Clock Stop OK(PS-ClkStopOK): This bit is not supported and will always return `0'b when read. Power State Error (PS-Error): This bit is not supported and will always return `0'b when read. Power State Actual (PS-Act): This field indicates the actual power state of the referenced node. The default state is D3.
DS880F1
99
CS4207
Power State Set (PS-Set): Writes to these bits set the Audio Function Group to the Power State as described below: PSS = '0000'b; D0 - Fully on. PSS = `0001'b; D1 - Not Supported PSS = `0010'b; D2 - Not Supported PSS = `0011'b; D3 - Allows for lowest possible power consumption under software control. See "D3 Lower Power State Support" on page 25 for more information. PSS = `0100'b; D4 - Not Supported
3:0
Read/Write
0011b
PS-Set is a PowerState field which defines the current power setting of the referenced node. Since this node is of type other than an Audio Function Group node, the actual power state is a function of both this setting and the PowerState setting of the Audio Function Group node under which this node was enumerated (is controlled). PS-Act is a PowerState field which indicates the actual power state of this node. Within the Audio Function Group node, this field will always be equal to the PS-Set field (modulo the time required to execute a power state transition). Within this type of node, this field will be the lower power consuming state of either a) the PS-Set field of the currently referenced node or b) the PS-Set field of the Audio Function Group node under which the currently referenced node was enumerated (is controlled).
6.11.7
Line In 1/Mic In 2 Pin Widget Control
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Ch Bits [19:8] Verb ID = F07h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Response Format: Bits 31:8 7 6 Type Read Only Read Only Read Only Default 0000h 0b 0b Description Reserved H-Phone Enable (HPE): Not supported on this widget. Output Enable (OUTE): Not supported on this widget. Input Enable (INE): This bit has no affect on the input path. Per HD Audio Spec, when `1', this bit enables the input path of the Pin Widget. When `0', the input path of the Pin Widget is shut off. Reserved VREF Enable (VREFE): Not supported on this widget. Bits [27:20] Node ID = 0Ch Bits [19:8] Verb ID = 707h Bits [7:0] Parameter ID = xxh
5 4:3 2:0
Read/Write Read Only Read Only
0b 00b 000b
100
DS880F1
CS4207
6.11.8 Mic In 1/Line In 2 Pin Widget Control
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Dh Bits [19:8] Verb ID = F07h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Response Format: Bits 31:8 7 6 Type Read Only Read Only Read/Write Default 0000h 0b 0b Reserved
H-Phone Enable (HPE): Not supported on this widget. Output Enable (OUTE): Not supported on this widget. Used by WHQL test to set VREFE = HiZ mode. Input Enable (INE): This bit has no affect on the input path. Per HD Audio Spec., when `1', this bit enables the input path of the Pin Widget. When set to `0', the input path of the Pin Widget will continue to operate.
Bits [27:20] Node ID = 0Dh
Bits [19:8] Verb ID = 707h
Bits [7:0] Parameter ID = xxh
Description
5
Read/Write
0b
4:3
Read Only
00b
Reserved
VREF Enable (VREFE): This field selects one of the possible states for the VREF signal(s). The pin associated with this function is MICBIAS. If the value written to this control does not correspond to a supported value (`000'b, `001'b, `010'b or `100'b), the VREFE bits must retain the previous value. `000'b = Hi-Z `001'b = 0.5*VA `010'b = GND `100'b = 0.8*VA
2:0
Read/Write
000b
6.11.9
Unsolicited Response Control
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
Line In 1 Node ID=0Ch Mic In 1 Node ID=0Dh
Bits [19:8] Verb ID = F08h
Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
Line In 1 Node ID=0Ch Mic In 1 Node ID=0Dh
Bits [19:8] Verb ID = 708h
Bits [7:0] Parameter ID = xxh[
Response Format
Bits [31:0] are sticky and will not be reset by a Link Reset or a Codec Reset:
Bits 31:8 Type Read Only Default 000000h Description Reserved
DS880F1
101
CS4207
7 6 Read/Write Read Only 0b 0b
Enable: Controls the actual generation of Unsolicited Responses. 1 is enable; 0 is disable. Reserved Tag: Is a 6 bit value assigned and used by software to determine what codec node generated the unsolicited response. The value programmed into the Tag field is returned in the top 6 bits (31:26) of every Unsolicited Response generated by this node.
5:0
Read/Write
000000b
Unsolicited Response Format :
Bits [31:26] Tag Bits [27:0] Response
6.11.10 Pin Sense
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
Line In 1 Node ID=0Ch Mic In 1 Node ID=0Dh
Bits [19:8] Verb ID = F09h
Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
Line In 1 Node ID=0Ch Mic In 1 Node ID=0Dh
Bits [19:8] Verb ID = 709h
Bits [7:0] Parameter ID = xxh
Get Response Format: Bits 31 Type Read Only Default 0b Description
Presence Detect (PDET): A `1' indicates that there is "something" plugged into the jack associated with the Pin Widget. A `0' indicates that nothing is plugged in. Impedance Sense (IMPS): Not valid since the widget is not capable of impedance sensing.
30:0
Read Only
0
Set Parameter ID [7:0] Format: Bits 7:1 0 Type Write Only Write Only Default 0000000b 0b Reserved
Right Channel (RCHAN): The write to this bit is ignored since the widget is not capable of impedance sensing.
Description
102
DS880F1
CS4207
6.11.11 Mic In 1/Line In 2 EAPD/BTL Enable
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Dh Bits [19:8] Verb ID = F0Ch Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Get Response Format: Bits 31:3 2 1 Type Read Only Read Only Read Only Default 0 0b 0b Reserved
L-R Swap: Not valid since the widget is not capable of left/right swapping. EAPD: Not supported on this widget. BTL: controls the input configuration of a Pin Widget which has indicated support for balanced I/O (bit 6, Pin Capabilities Parameter). When this bit is 0, the inputs are configured in single-ended or pseudo-differential mode; when this bit is 1, they are configured in balanced (fully differential) mode. Note: This bit is OR'ed with the ADC2 Gain bit in the ADC Configuration (CIR = 0002h) Register of the Vendor Processing Widget (Node
Bits [27:20] Node ID = 0Dh
Bits [19:8] Verb ID = 70Ch
Bits [7:0] Parameter ID = xxh
Description
0
Read/Write
0b
ID = 11h).
6.11.12 Line In 1/Mic In 2 Configuration Default
The Configuration Default register is used by software as an aid in determining the configuration of jacks and devices attached to the codec. At the time the codec is first powered on, this register is internally loaded with default values indicating the typical system use of this particular pin/jack. After this initial loading, it is completely codec opaque, and its state, including any software writes into the register, must be preserved across reset events such as LINK Reset or Codec Reset (the Function Reset Verb). Its state need not be preserved across power level changes. Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Ch Bits [19:8] Verb ID = F1Ch Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Ch Bits [19:8] Verb ID = 71Ch Verb ID = 71Dh Verb ID = 71Eh Verb ID = 71Fh Bits [7:0] Parameter ID = xxh[7:0] Parameter ID = xxh[15:8] Parameter ID = xxh[23:16] Parameter ID = xxh[31:24]
Response Format Bits [31:0] are sticky and will not be reset by a Link Reset or a Codec Reset:
Bits Type Default Description
DS880F1
103
CS4207
31:30 29:24 23:20 19:16 15:12 11:8 Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write 00b 000001b 8h 1h 3h 0h
Port Connectivity (PCON): The external connectivity of this Pin Widget is a jack. Location (LOC): This field indicates the physical location of the jack to which the pin complex is connected. Set to external rear-panel. Default Device (DD): Indicates the intended use of the connection is for line in. Connection Type (CTYP): Indicates the type of physical connection is 1/8" jack. Color (COL): This field indicates the color of the physical jack for use by software. The color selected is blue. Miscellaneous (MISC): No PDC override. Default Association (DA): This field is used by software to group Pin Complex (and therefore jacks) together into functional blocks to support multichannel operation. All jacks with the same association number may be assumed to be grouped together. A value of all `0's is reserved. A value of all `1's in this field indicates that the Association has the lowest priority. Sequence (SEQ): This field indicates the order of the jacks in the association group.
7:4
Read/Write
5h
3:0
Read/Write
1h
6.11.13 Mic In 1/Line In 2 Configuration Default
The Configuration Default register is used by software as an aid in determining the configuration of jacks and devices attached to the codec. At the time the codec is first powered on, this register is internally loaded with default values indicating the typical system use of this particular pin/jack. After this initial loading, it is completely codec opaque, and its state, including any software writes into the register, must be preserved across reset events such as LINK Reset or Codec Reset (the Function Reset Verb). Its state need not be preserved across power level changes. Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Dh Bits [19:8] Verb ID = F1Ch Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Dh Bits [19:8] Verb ID = 71Ch Verb ID = 71Dh Verb ID = 71Eh Verb ID = 71Fh Bits [7:0] Parameter ID = xxh[7:0] Parameter ID = xxh[15:8] Parameter ID = xxh[23:16] Parameter ID = xxh[31:24]
Response Format
Bits [31:0] are sticky and will not be reset by a Link Reset or a Codec Reset:
Bits 31:30 29:24 Type Read/Write Read/Write Default 00b 000001b Description
Port Connectivity (PCON): The external connectivity of this Pin Widget is a jack. Location (LOC): This field indicates the physical location of the jack to which the pin complex is connected. Set to external rear-panel.
104
DS880F1
CS4207
23:20 19:16 15:12 11:8 Read/Write Read/Write Read/Write Read/Write Ah 1h 9h 0h
Default Device (DD): Indicates the intended use of the connection is for Mic in. Connection Type (CTYP): Indicates the type of physical connection is 1/8" jack. Color (COL): This field indicates the color of the physical jack for use by software. The color selected is pink. Miscellaneous (MISC): No PDC override. Default Association (DA): This field is used by software to group Pin Complex (and therefore jacks) together into functional blocks to support multichannel operation. All jacks with the same association number may be assumed to be grouped together. A value of all `0's is reserved. A value of all `1's in this field indicates that the Association has the lowest priority. Sequence (SEQ): This field indicates the order of the jacks in the association group.
7:4
Read/Write
3h
3:0
Read/Write
1h
6.11.14 Amplifier Gain/Mute
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
Line In 1 Node ID=0Ch Mic In 1 Node ID=0Dh
Bits [19:8] Verb ID = Bxxh
Bits [7:0] Parameter ID = xxh
Bits [19:8] = `Bxxxx', where bits [15:0] are defined below:
Bits [15:0] 15 14 13 12:4 3:0 Value 0b 0b xb 000000000b 0000b Description
Get Output/Input (GOI): This bit controls whether the request is for the input amplifier or the output amplifier. When `1', the output amplifier is being requested. When `0', the input amplifier is being requested.
`0'b
Get Left/Right (GLR): This bit controls whether the request is for the left channel amplifier or the right channel amplifier. When `1', the left channel amplifier is being requested. When `0', the right channel amplifier is being requested.
Reserved
Index (IDX): This field specifies the input index of the amplifier setting to return if the widget has multiple input amplifiers. This field has no meaning and ignored since the widget does not have multiple input amplifiers. It should be always `0's.
Response Format:
Bits 31:8 7 Type Read Only Read Only Default 000000h 0b Description Always returned "000000h"
Amplifier Mute (AM): Mute is not supported by this widget. Amplifier Gain (AG): This field returns the Gain setting for the amplifier requested. If the amplifier requested does not exist, all `0's will be returned. Default equals 0 dB.
6:0
Read Only
0000000b
DS880F1
105
CS4207
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
Line In 1 Node ID=0Ch Mic In 1 Node ID=0Dh
Bits [19:8] Verb ID = 3xxh
Bits [7:0] Parameter ID = xxh
Bits [19:8] = `3xxxx', where bits [15:0] are defined below:
Bits Type Default Description
Set Output Amplifier (SOA): This bit determines whether the value programmed refers to the output amplifier. This bit should always be `0' since an output amplifier is not present on this widget. Set Input Amplifier (SIA): This bit determines whether the value programmed refers to the input amplifier. Set to a 1 for the value to be accepted. Set Left Amplifier (SLA): Selects the left channel (channel 0). A 1 indicates that the relevant amplifier should accept the value being set. If both bits are set, both amplifiers are set. Set Right Amplifier (SRA): Selects the right channel (channel 1). A 1 indicates that the relevant amplifier should accept the value being set. If both bits are set, both amplifiers are set. Index (IDX): This field is used when programming the input amplifiers on Selector Widgets and Sum Widgets. This field is ignored. Mute (MUTE): When `0', the Mute is inactive. This field is ignored. Gain (GAIN): Specifies the amplifier gain in dB. xxxxx00b = 0dB xxxxx01b = +10dB xxxxx10b = +20dB xxxxx11b = +30dB Bits(6:2) are not used and are ignored.
15
Write Only
0b
14
Write Only
xb
13
Write Only
xb
12
Write Only
xb
11:8 7
Write Only Write Only
0000b 0b
6:0
Write Only
xxxxxxxb
106
DS880F1
CS4207
6.12 Digital Mic In 1, Digital Mic In 2 Pin Widgets (Node ID = 0Eh, 12h)
6.12.1 Audio Widget Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
DigMic 1 Node ID=0Eh DigMic 2 Node ID=12h
Bits [19:8] Verb ID = F00h
Bits [7:0] Parameter ID = 09h
Response Format:
Bits 31:24 23:20 19:16 15:12 11 10 9 8 7 6 5 4 3 2 1 0 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 00h 4h 1h 0h 0b 0b 0b 0b 0b 0b 0b 0b 1b 0b 1b 1b Reserved
Type (TYP): Pin Complex Widget Delay (DLY): Number of sample delays through the widget.
Description
Reserved
L-R Swap (LRS): This widget is not capable of swapping the left and right channels. Power Control (PC): Power State control is not supported on this widget. Digital (DIG): Widget is not a digital widget. Connection List (CL): A connection list is not present on this widget. Unsolicited Capable (UC): Unsolicited Response is not supported on this widget. Processing Widget (PW): This widget does not contain "Processing Controls" parameters. Stripe (STRP): Stripping is not supported. Format Override (FO): This widget does not contain format information. Amplifier Parameter Override (APO): This widget contains its own amplifier parameters. Output Amplifier Present (OAP): Output amplifier is not present for this widget. Input Amplifier Present (IAP): Input amplifier is present for this widget. Stereo (ST): A 1 indicates a stereo widget.
DS880F1
107
CS4207
6.12.2 Pin Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
DigMic 1 Node ID=0Eh DigMic 2 Node ID=12h
Bits [19:8] Verb ID = F00h
Bits [7:0] Parameter ID = 0Ch
Response Format:
Bits 31:17 16 15:8 7 6 5 4 3 2 1 0 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 0 0b 00h 0b 0b 1b 0b 0b 0b 0b 0b Reserved
EAPD Capable (EAPDC): EAPD not supported. VREF Control (VREFC): VREF not supported. HDMI Capable (HDMIC): HDMI is not supported Balanced I/O Pins (BIOP): This widget does not have balanced I/O pins. Input Capable (INC): Input capable. Output Capable (OUTC): Not output capable. Headphone Drive Capable (HDC): Widget is not capable of driving headphones directly. Presence Detect Capable (PDC): This bit is `0' to indicate that the widget is not capable of performing presence detect. Trigger Required (TR): Trigger is not required for an impedance measurement. Impedance Sense Capable (ISC): This bit is `0' to indicate that the widget does not support impedance sense on the attached peripheral.
Description
6.12.3 Input Amplifier Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
DigMic 1 Node ID=0Eh DigMic 2 Node ID=12h
Bits [19:8] Verb ID = F00h
Bits [7:0] Parameter ID = 0Dh
Response Format:
Bits 31 30:23 22:16 15 14:8 7 6:0 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 0b 00000000b 0100111b 0b 0000010b 0b 0000000b Reserved
Step Size (SS): Indicates that the size of each amplifier's step gain is 10dB
Description
Mute Capable (MC): Does not support mute.
Reserved
Number of Steps (NOS): There are 3 gain steps; 0dB, +10dB and +20dB.
Reserved
Offset (OFST): Indicates that if "0000000b" is programmed into the Amplified Gain Control, it would result in a gain of 0dB.
108
DS880F1
CS4207
6.12.4 Pin Widget Control
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
DigMic 1 Node ID=0Eh DigMic 2 Node ID=12h
Bits [19:8] Verb ID = F07h
Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
DigMic 1 Node ID=0Eh DigMic 2 Node ID=12h
Bits [19:8] Verb ID = 707h
Bits [7:0] Parameter ID = xxh
Response Format: Bits 31:8 7 6 5 4:3 2:0 Type Read Only Read Only Read Only Read/Write Read Only Read Only Default 0000h 0b 0b 0b 00b 000b
Reserved H-Phone Enable (HPE): Not supported. Output Enable (OUTE): Not supported. Input Enable (INE): This bit, when set to `1', enables the data path for the corresponding DMIC. When set to `0', the data path is disabled and the corresponding ADC output is muted.
Description
Reserved
VREF Enable (VREFE): VREF is not supported on this widget. Will always read back `000'
6.12.5 Digital Mic In 1 Configuration Default
The Configuration Default register is used by software as an aid in determining the configuration of jacks and devices attached to the codec. At the time the codec is first powered on, this register is internally loaded with default values indicating the typical system use of this particular pin/jack. After this initial loading, it is completely codec opaque, and its state, including any software writes into the register, must be preserved across reset events such as LINK Reset or Codec Reset (the Function Reset Verb). Its state need not be preserved across power level changes. Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Eh Bits [19:8] Verb ID = F1Ch Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Eh Bits [19:8] Verb ID = 71Ch Verb ID = 71Dh Verb ID = 71Eh Verb ID = 71Fh Bits [7:0] Parameter ID = xxh[7:0] Parameter ID = xxh[15:8] Parameter ID = xxh[23:16] Parameter ID = xxh[31:24]
Response Format Bits [31:0] are sticky and will not be reset by a Link Reset or a Codec Reset:
Bits 31:30 Type Read/Write Default 10b Description
Port Connectivity (PCON): A fixed function device is attached.
DS880F1
109
CS4207
29:24 23:20 19:16 15:12 11:8 Read/Write Read/Write Read/Write Read/Write Read/Write 110111b Dh 6h 0h 0h
Location (LOC): This field indicates the physical location of the device to which the pin complex is connected. Set to internal + mobile lid inside. Default Device (DD): Indicates the intended use of the connection is for Digital In. Connection Type (CTYP): Indicates the type of physical connection is Other Digital. Color (COL): This field indicates the color of the physical jack for use by software. The color selected is unknown. Miscellaneous (MISC): No PDC override. Default Association (DA): This field is used by software to group Pin Complex (and therefore jacks) together into functional blocks to support multichannel operation. All jacks with the same association number may be assumed to be grouped together. A value of all `0's is reserved. A value of all `1's in this field indicates that the Association has the lowest priority. Sequence (SEQ): This field indicates the order of the jacks in the association group.
7:4
Read/Write
3h
3:0
Read/Write
Eh
6.12.6 Digital Mic In 2 Configuration Default
The Configuration Default register is used by software as an aid in determining the configuration of jacks and devices attached to the codec. At the time the codec is first powered on, this register is internally loaded with default values indicating the typical system use of this particular pin/jack. After this initial loading, it is completely codec opaque, and its state, including any software writes into the register, must be preserved across reset events such as LINK Reset or Codec Reset (the Function Reset Verb). Its state need not be preserved across power level changes. Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 12h Bits [19:8] Verb ID = F1Ch Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 12h Bits [19:8] Verb ID = 71Ch Verb ID = 71Dh Verb ID = 71Eh Verb ID = 71Fh Bits [7:0] Parameter ID = xxh[7:0] Parameter ID = xxh[15:8] Parameter ID = xxh[23:16] Parameter ID = xxh[31:24]
Response Format Bits [31:0] are sticky and will not be reset by a Link Reset or a Codec Reset:
Bits 31:30 29:24 23:20 Type Read/Write Read/Write Read/Write Default 10b 110111b Dh Description
Port Connectivity (PCON): A fixed function device is attached. Location (LOC): This field indicates the physical location of the device to which the pin complex is connected. Set to internal + mobile lid inside. Default Device (DD): Indicates the intended use of the connection is for Digital In.
110
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19:16 15:12 11:8 Read/Write Read/Write Read/Write 6h 0h 0h
Connection Type (CTYP): Indicates the type of physical connection is Other Digital. Color (COL): This field indicates the color of the physical jack for use by software. The color selected is unknown. Miscellaneous (MISC): No PDC override. Default Association (DA): This field is used by software to group Pin Complex (and therefore jacks) together into functional blocks to support multichannel operation. All jacks with the same association number may be assumed to be grouped together. A value of all `0's is reserved. A value of all `1's in this field indicates that the Association has the lowest priority. Sequence (SEQ): This field indicates the order of the jacks in the association group.
7:4
Read/Write
5h
3:0
Read/Write
Eh
6.12.7 Amplifier Gain/Mute
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
DigMic 1 Node ID=0Eh DigMic 2 Node ID=12h
Bits [19:8] Verb ID = Bxxh
Bits [7:0] Parameter ID = xxh
Bits [19:8] = `Bxxxx', where bits [15:0] are defined below:
Bits [15:0] 15 14 13 12:4 3:0 Value 0b 0b xb 000000000b 0000b Description
Get Output/Input (GOI): This bit controls whether the request is for the input amplifier or the output amplifier. When `1', the output amplifier is being requested. When `0', the input amplifier is being requested.
`0'b
Get Left/Right (GLR): This bit controls whether the request is for the left channel amplifier or the right channel amplifier. When `1', the left channel amplifier is being requested. When `0', the right channel amplifier is being requested.
Reserved
Index (IDX): This field specifies the input index of the amplifier setting to return if the widget has multiple input amplifiers. This field has no meaning and ignored since the widget does not have multiple input amplifiers. It should be always `0's.
Response Format:
Bits 31:8 7 Type Read Only Read Only Default 000000h 0b Description Always returned "000000h"
Amplifier Mute (AM): Mute is not supported by this widget. Amplifier Gain (AG): This field returns the Gain setting for the amplifier requested. If the amplifier requested does not exist, all `0's will be returned. Default equals 0 dB.
6:0
Read Only
0000000b
Set Parameter Command Format:
Bits [31:28] Bits [27:20] Bits [19:8] Bits [7:0]
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CAd = X
DigMic 1 Node ID=0Eh DigMic 2 Node ID=12h
Verb ID = 3xxh
Parameter ID = xxh
Bits [19:8] = `3xxxx', where bits [15:0] are defined below:
Bits 15 Type Write Only Default 0b Description
Set Output Amplifier (SOA): This bit determines whether the value programmed refers to the output amplifier. This bit should always be `0' since an output amplifier is not present. Set Input Amplifier (SIA): This bit determines whether the value programmed refers to the input amplifier. Set to 1 for the value to be accepted. Set Left Amplifier (SLA): Selects the left channel (channel 0). A 1 indicates that the relevant amplifier should accept the value being set. If both bits are set, both amplifiers are set. Set Right Amplifier (SRA): Selects the right channel (channel 1). A 1 indicates that the relevant amplifier should accept the value being set. If both bits are set, both amplifiers are set. Index (IDX): This field is used when programming the input amplifiers on Selector Widgets and Sum Widgets. This field is ignored. Mute (MUTE): When `0', the Mute is inactive. This field is ignored. Gain (GAIN): Specifies the amplifier gain in dB. xxxxx00b = 0dB xxxxx01b = +10dB xxxxx10b = +20dB xxxxx11b = not used Bits(6:2) are not used and are ignored.
14
Write Only
xb
13
Write Only
xb
12
Write Only
xb
11:8 7
Write Only Write Only
0000b 0b
6:0
Write Only
xxxxxxxb
112
DS880F1
CS4207
6.13 S/PDIF Receiver Input Pin Widget (Node ID = 0Fh)
6.13.1 Audio Widget Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Fh Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 09h
Response Format:
Bits 31:24 23:20 19:16 15:12 11 10 9 8 7 6 5 4 3 2 1 0 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 00h 4h 1h 0h 0b 1b 1b 0b 1b 0b 0b 0b 0b 0b 0b 1b Reserved
Type (TYP): Pin Complex Widget Delay (DLY): Number of sample delays through the widget.
Description
Reserved
L-R Swap (LRS): This widget is not capable of swapping the left and right channels. Power Control (PC): Power State control is supported on this widget. Digital (DIG): Widget is a digital widget. Connection List (CL): A connection list is not present on this widget. Unsolicited Capable (UC): Unsolicited Response is supported on this widget. Processing Widget (PW): This widget does not contain "Processing Controls" parameters. Stripe (STRP): Stripping is not supported. Format Override (FO): This widget does not contain format information. Amplifier Parameter Override (APO): This widget does not contain amplifier parameters. Output Amplifier Present (OAP): Output amplifier is not present for this widget. Input Amplifier Present (IAP): Input amplifier is not present for this widget. Stereo (ST): A 1 indicates a stereo widget.
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6.13.2 Pin Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Fh Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Ch
Response Format:
Bits 31:17 16 15:8 7 6 5 4 3 2 1 0 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 0 0b 00h 0h 0b 1b 0b 0b 1b 0b 0b Reserved
EAPD Capable (EAPDC): EAPD not supported. VREF Control (VREFC): VREF not supported. HDMI Capable (HDMIC): HDMI not supported. Balanced I/O Pins (BIOP): This widget does not have balanced I/O pins. Input Capable (INC): Widget is input capable. Output Capable (OUTC): Is not output capable. Headphone Drive Capable (HDC): Widget is not capable of driving headphones directly. Presence Detect Capable (PDC): This bit is `1' to indicate that the widget is capable of performing presence detect. Trigger Required (TR): Trigger is not required for an impedance measurement. Impedance Sense Capable (ISC): A `0' indicates that the widget does not support impedance sense on the attached peripheral.
Description
6.13.3 Supported Power States
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Fh Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 0Fh
Response Format:
Bits 31 Type Read Only Default 1b Description EPSS Supported. Indicates that this pin wid-
get supports additional capabilities allowing better low power operation.
30 29:5 4 3 Read Only Read Only Read Only Read Only 0b 000000h 0b 1b Reserved Reserved D4 is not Supported D3 is Supported. Since Extended Power States is also supported, the pin widget will maintain the ability to generate an Unsolicited Response (if this function is enabled) while in the D3 state. D2 is not Supported D1 is not Supported D0 Supported
2 1 0
Read Only Read Only Read Only
0b 0b 1b
114
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6.13.4 Power States
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Fh Bits [19:8] Verb ID = F05h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Fh Bits [19:8] Verb ID = 705h Bits [7:0] Parameter ID = 0xh
Response Format:
Bits 31:11 Type Read Only Default 00000h Reserved
Power State Settings Reset (PS-SettingsReset): This bit is set to `1'b when, during any type of reset or low power state transition, the settings within this widget that were changed from the defaults, either by software or hardware, have been reset back to their default state. When these settings have not been reset, this is reported as `0'b. This bit is always a `1'b following a POR condition. For more information,
Description
10
Read Only
1b
see "Power State Settings Reset (PS-SettingsReset)" on p 27
9 8 7:4 Read Only Read Only Read Only 0b 0b 0011b
Power State Clock Stop OK(PS-ClkStopOK): This bit is not supported and will always return `0'b when read. Power State Error (PS-Error): This bit is not supported and will always return `0'b when read. Power State Actual (PS-Act): This field indicates the actual power state of the referenced node. The default state is D3. Power State Set (PS-Set): Writes to these bits set the Audio Function Group to the Power State as described below: PSS = '0000'b; D0 - Fully on. PSS = `0001'b; D1 - Not Supported PSS = `0010'b; D2 - Not Supported PSS = `0011'b; D3 - Allows for lowest possible power consumption under software control. See "D3 Lower Power State Support" on page 25 for more information. PSS = `0100'b; D4 - Not Supported
3:0
Read/Write
0011b
PS-Set is a PowerState field which defines the current power setting of the referenced node. Since this node is of type other than an Audio Function Group node, the actual power state is a function of both this setting and the PowerState setting of the Audio Function Group node under which this node was enumerated (is controlled). PS-Act is a PowerState field which indicates the actual power state of this node. Within the Audio Function Group node, this field will always be equal to the PS-Set field (modulo the time required to execute a power state transition). Within this type of node, this field will be the lower power consuming state of either
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a) the PS-Set field of the currently referenced node or b) the PS-Set field of the Audio Function Group node under which the currently referenced node was enumerated (is controlled).
6.13.5 Pin Widget Control
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Fh Bits [19:8] Verb ID = F07h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Response Format: Bits 31:8 7 6 Type Read Only Read Only Read Only Default 0000h 0b 0b Reserved
H-Phone Enable (HPE): Not supported on this widget. Output Enable (OUTE): Not supported on this widget. Input Enable (INE): This bit has no affect on the input path. Per HD Audio Spec., when `1', this bit enables the input path of the Pin Widget. When `0', the input path of the Pin Widget is shut off.
Bits [27:20] Node ID = 0Fh
Bits [19:8] Verb ID = 707h
Bits [7:0] Parameter ID = xxh
Description
5 4:3 2:0
Read/Write Read Only Read Only
0b 00b 000b
Reserved
VREF Enable (VREFE): VREF is not supported on this widget. These bits are ignored and always report `000'.
6.13.6 Unsolicited Response Control
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Fh Bits [19:8] Verb ID = F08h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Response Format Bits [27:20] Node ID = 0Fh Bits [19:8] Verb ID = 708h Bits [7:0] Parameter ID = xxh[
Bits [31:0] are sticky and will not be reset by a Link Reset or a Function Group Reset:
Bits 31:8 Type Read Only Default 000000h Reserved Description
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7 Read/Write 0b
Enable: Determines if a change in receiver lock status will generate an Unsolicited Response (0 = No, 1 = Yes). If enabled, and the lock status changes from "LOCK" to "UNLOCK" or "UNLOCK" to "LOCK", an unsolicited response will be sent. The default value after cold or register reset for this register (0b) specifying no unsolicited response.
6 5:0
Read Only Read/Write
0b 000000b
Reserved
Tag: Is a 6-bit value assigned and used by software to determine what codec node generated the unsolicited response. The value programmed into the Tag field is returned in the top 6 bits (31:26) of every Unsolicited Response generated by this node.
Unsolicited Response Format :
Bits [31:26] Tag Bits [27:0] Response
6.13.7 Pin Sense
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Fh Bits [19:8] Verb ID = F09h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Get Response Format: Bits 31 Type Read Only Default 0b Description
Presence Detect (PDET): A `1' indicates that there is "something" plugged into the jack associated with the Pin Widget. A `0' indicates that nothing is plugged in. Impedance Sense (IMPS): Not valid since the widget is not capable of impedance sensing.
Bits [27:20] Node ID = 0Fh
Bits [19:8] Verb ID = 709h
Bits [7:0] Parameter ID = xxh
30:0
Read Only
0
Set Parameter ID [7:0] Format:
Bits 7:1 0 Type Write Only Write Only Default 0000000b 0b Reserved
Right Channel (RCHAN): The write to this bit is ignored since the widget is not capable of impedance sensing.
Description
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6.13.8 Configuration Default
The Configuration Default register is used by software as an aid in determining the configuration of jacks and devices attached to the codec. At the time the codec is first powered on, this register is internally loaded with default values indicating the typical system use of this particular pin/jack. After this initial loading, it is completely codec opaque, and its state, including any software writes into the register, must be preserved across reset events such as LINK Reset or Codec Reset (the Function Reset Verb). Its state need not be preserved across power level changes. Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Fh Bits [19:8] Verb ID = F1Ch Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 0Fh Bits [19:8] Verb ID = 71Ch Verb ID = 71Dh Verb ID = 71Eh Verb ID = 71Fh Bits [7:0] Parameter ID = xxh[7:0] Parameter ID = xxh[15:8] Parameter ID = xxh[23:16] Parameter ID = xxh[31:24]
Response Format
Bits [31:0] are sticky and will not be reset by a Link Reset or a Codec Reset:
Bits 31:30 29:24 23:20 19:16 15:12 11:8 Type Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Default 00b 000010b Ch 4h Eh 0h Description
Port Connectivity (PCON): The external connectivity of this Pin Widget is a jack. Location (LOC): This field indicates the physical location of the jack to which the pin complex is connected. Set to external front-panel. Default Device (DD): Indicates the intended use of the connection is for S/PDIF in. Connection Type (CTYP): Indicates the type of physical connection is RCA jack. Color (COL): This field indicates the color of the physical jack for use by software. The color selected is white. Miscellaneous (MISC): No PDC override. Default Association (DA): This field is used by software to group Pin Complex (and therefore jacks) together into functional blocks to support multichannel operation. All jacks with the same association number may be assumed to be grouped together. A value of all `0's is reserved. A value of all `1's in this field indicates that the Association has the lowest priority. Sequence (SEQ): This field indicates the order of the jacks in the association group.
7:4
Read/Write
Fh
3:0
Read/Write
0h
118
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6.14 S/PDIF Transmitter 1, S/PDIF Transmitter 2 Output Pin Widgets (Node ID = 10h, 15h)
6.14.1 Audio Widget Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
S/P Tx 1 Node ID=10h S/P Tx 2 Node ID=15h
Bits [19:8] Verb ID = F00h
Bits [7:0] Parameter ID = 09h
Response Format:
Bits 31:24 23:20 19:16 15:12 11 10 9 8 7 6 5 4 3 2 1 0 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 00h 4h 1h 0h 0b 0b 1b 1b 0b 0b 0b 0b 0b 0b 0b 1b Reserved
Type (TYP): Pin Complex Widget Delay (DLY): Number of sample delays through the widget.
Description
Reserved
L-R Swap (LRS): This widget is not capable of swapping the left and right channels. Power Control (PC): Power State control is not supported on this widget. Digital (DIG): Widget is a digital widget. Connection List (CL): A connection list is present on this widget. Unsolicited Capable (UC): Unsolicited Response is not supported on this widget. Processing Widget (PW): This widget does not contain "Processing Controls" parameters. Stripe (STRP): Stripping is not supported. Format Override (FO): This widget does not contain format information. Amplifier Parameter Override (APO): This widget does not contain amplifier parameters. Output Amplifier Present (OAP): Output amplifier is not present for this widget. Input Amplifier Present (IAP): Input amplifier is not present for this widget. Stereo (ST): A 1 indicates a stereo widget.
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6.14.2 Pin Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
S/P Tx 1 Node ID=10h S/P Tx 2 Node ID=15h
Bits [19:8] Verb ID = F00h
Bits [7:0] Parameter ID = 0Ch
Response Format:
Bits 31:17 16 15:8 7 6 5 4 3 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 0 0b 00h 0h 0b 0b 1b 0b Reserved
EAPD Capable (EAPDC): EAPD not supported. VREF Control (VREFC): VREF not supported. HDMI Capable (HDMIC): HDMI not supported. Balanced I/O Pins (BIOP): This widget does not have balanced I/O pins. Input Capable (INC): Widget is not input capable. Output Capable (OUTC): This bit is `1' to indicate that the widget is output capable. Headphone Drive Capable (HDC): Widget is not capable of driving headphones directly. Presence Detect Capable (PDC): This bit is `0' to indicate that the widget is not capable of performing presence detect to determine whether there is anything plugged in. Trigger Required (TR): Trigger is not required for an impedance measurement. Impedance Sense Capable (ISC): This bit is `0' to indicate that the widget does not support impedance sense on the attached peripheral.
Description
2
Read Only
0b
1 0
Read Only Read Only
0b 0b
6.14.3 Connection List Length
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
S/P Tx 1 Node ID=10h S/P Tx 2 Node ID=15h
Bits [19:8] Verb ID = F00h
Bits [7:0] Parameter ID = 0Eh
Response Format:
Bits 31:8 7 6:0 Type Read Only Read Only Read Only Default 000000h 0b 0000001b Reserved
Long Form (LF): Connection list is short form. Connection List Length (CLL): One hard-wired input for this widget.
Description
120
DS880F1
CS4207
6.14.4 S/PDIF Transmitter 1 Connection List Entry
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 10h Bits [19:8] Verb ID = F02h Bits [7:0] Parameter ID = N=00h
Response Format:
Bits 31:24 23:16 15:8 7:0 Type Read Only Read Only Read Only Read Only Default 00h 00h 00h 08h Description
Connection List Entry (N+3): Returns 00h for N=00h-03h or N>03h. Connection List Entry (N+2): Returns 00h for N=00h-03h or N>03h. Connection List Entry (N+1): Returns 00h for N=00h-03h or N>03h. Connection List Entry (N): Returns 08h (S/PDIF Out 1) for N=00h-03h. Returns 00h for N>03h.
6.14.5 S/PDIF Transmitter 2 Connection List Entry
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 15h Bits [19:8] Verb ID = F02h Bits [7:0] Parameter ID = N=00h
Response Format:
Bits 31:24 23:16 15:8 7:0 Type Read Only Read Only Read Only Read Only Default 00h 00h 00h 14h Description
Connection List Entry (N+3): Returns 00h for N=00h-03h or N>03h. Connection List Entry (N+2): Returns 00h for N=00h-03h or N>03h. Connection List Entry (N+1): Returns 00h for N=00h-03h or N>03h. Connection List Entry (N): Returns 14h (S/PDIF Out 2) for N=00h-03h. Returns 00h for N>03h.
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6.14.6 Pin Widget Control
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
S/P Tx 1 Node ID=10h S/P Tx 2 Node ID=15h
Bits [19:8] Verb ID = F07h
Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20]
S/P Tx 1 Node ID=10h S/P Tx 2 Node ID=15h
Bits [19:8] Verb ID = 707h
Bits [7:0] Parameter ID = xxh
Response Format: Bits 31:8 7 6 Type Read Only Read Only Read/Write Default 0000h 0b 0b Reserved
H-Phone Enable (HPE): Not supported. Output Enable (OUTE): This bit has no affect on the output path. Per HD Audio Spec., when `1', this bit enables the output path of the Pin Widget. When `0', the output path is shut off. Input Enable (INE): Set to `0' since there is no input path associated with the pin widget.
Description
5 4:3 2:0
Read Only Read Only Read Only
0b 00b 000b
Reserved
VREF Enable (VREFE): The Pin Widget does not support VREF generation as indicated in the Pin Capabilities. As such, this field should always be "000b" to select the Hi-Z state.
122
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CS4207
6.14.7 S/PDIF Transmitter 1 Configuration Default
The Configuration Default register is used by software as an aid in determining the configuration of jacks and devices attached to the codec. At the time the codec is first powered on, this register is internally loaded with default values indicating the typical system use of this particular pin/jack. After this initial loading, it is completely codec opaque, and its state, including any software writes into the register, must be preserved across reset events such as LINK Reset or Codec Reset (the Function Reset Verb). Its state need not be preserved across power level changes. Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 10h Bits [19:8] Verb ID = F1Ch Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 10h Bits [19:8] Verb ID = 71Ch Verb ID = 71Dh Verb ID = 71Eh Verb ID = 71Fh Bits [7:0] Parameter ID = xxh[7:0] Parameter ID = xxh[15:8] Parameter ID = xxh[23:16] Parameter ID = xxh[31:24]
Response Format
Bits [31:0] are sticky and will not be reset by a Link Reset or a Codec Reset:
Bits 31:30 Type Read/Write Default 00b Description
Port Connectivity (PCON): The external connectivity of this Pin Widget is a jack. Location (LOC): This field indicates the physical location of the jack or device to which the pin complex is connected. Set to External Rear Panel. Default Device (DD): Indicates the intended use of the jack is for S/PDIF Out. Connection Type (CTYP): Indicates the type of physical connection is an RCA jack. Color (COL): This field indicates the color of the physical jack for use by software. The color selected is Orange. Miscellaneous (MISC): No PDC override. Default Association (DA): This field is used by software to group Pin Complex (and therefore jacks) together into functional blocks to support multichannel operation. All jacks with the same association number may be assumed to be grouped together. A value of all `0's is reserved. A value of all `1's in this field indicates that the Association has the lowest priority. Sequence (SEQ): This field indicates the order of the jacks in the association group.
29:24
Read/Write
000001b
23:20 19:16 15:12 11:8
Read/Write Read/Write Read/Write Read/Write
4h 4h 6h 0h
7:4
Read/Write
Fh
3:0
Read/Write
0h
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6.14.8 S/PDIF Transmitter 2 Configuration Default
The Configuration Default register is used by software as an aid in determining the configuration of jacks and devices attached to the codec. At the time the codec is first powered on, this register is internally loaded with default values indicating the typical system use of this particular pin/jack. After this initial loading, it is completely codec opaque, and its state, including any software writes into the register, must be preserved across reset events such as LINK Reset or Codec Reset (the Function Reset Verb). Its state need not be preserved across power level changes. Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 15h Bits [19:8] Verb ID = F1Ch Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 15h Bits [19:8] Verb ID = 71Ch Verb ID = 71Dh Verb ID = 71Eh Verb ID = 71Fh Bits [7:0] Parameter ID = xxh[7:0] Parameter ID = xxh[15:8] Parameter ID = xxh[23:16] Parameter ID = xxh[31:24]
Response Format
Bits [31:0] are sticky and will not be reset by a Link Reset or a Codec Reset:
Bits 31:30 Type Read/Write Default 00b Description
Port Connectivity (PCON): The external connectivity of this Pin Widget is a jack. Location (LOC): This field indicates the physical location of the jack or device to which the pin complex is connected. Set to External Rear Panel. Default Device (DD): Indicates the intended use of the jack is for S/PDIF Out. Connection Type (CTYP): Indicates the type of physical connection is an optical TOSLINK jack. Color (COL): This field indicates the color of the physical jack for use by software. The color selected is Black. Miscellaneous (MISC): No PDC override. Default Association (DA): This field is used by software to group Pin Complex (and therefore jacks) together into functional blocks to support multichannel operation. All jacks with the same association number may be assumed to be grouped together. A value of all `0's is reserved. A value of all `1's in this field indicates that the Association has the lowest priority. Sequence (SEQ): This field indicates the order of the jacks in the association group.
29:24
Read/Write
000001b
23:20 19:16 15:12 11:8
Read/Write Read/Write Read/Write Read/Write
4h 5h 1h 0h
7:4
Read/Write
Fh
3:0
Read/Write
0h
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6.15 Vendor Processing Widget (Node ID = 11h)
6.15.1 Audio Widget Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 11h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 09h
Response Format:
Bits 31:24 23:20 19:16 15:12 11 10 9 8 7 6 5 4 3 2 1 0 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 00h Fh 0h 0h 0b 0b 0b 0b 0b 1b 0b 0b 0b 0b 0b 0b Reserved
Type (TYP): Vendor Defined Widget Delay (DLY): Number of sample delays through the widget.
Description
Reserved
L-R Swap (LRS): This widget is not capable of swapping the left and right channels. Power Control (PC): Power State control is not supported on this widget. Digital (DIG): Widget is not a digital widget. Connection List (CL): Connection list is not present. Unsolicited Capable (UC): Not supported. Processing Widget (PW): Widget does contain "Processing Controls" parameters. Stripe (STRP): Stripping is not supported. Format Override (FO): Set to `0' to indicate that the widget does not contain format information. Amplifier Parameter Override (APO): This widget does not contain amplifier parameters. Output Amplifier Present (OAP): Not present. Input Amplifier Present (IAP): Input amplifier is not present for this widget. Stereo (ST): A 0 indicates not supported.
6.15.2 Processing Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 11h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 10h
Response Format:
Bits 31:16 15:8 7:1 0 Type Read Only Read Only Read Only Read Only Default 0000h 16h 0000000b 0b Reserved
NumCoeff: Number of coefficients. There are a total of 22 registers.
Description
Reserved
Benign: This processing widget is not linear and time invariant.
DS880F1
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CS4207
6.15.3 Processing State
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 11h Bits [19:8] Verb ID = F03h Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 11h Bits [19:8] Verb ID = 703h Bits [7:0] Parameter ID = xxh
Response Format:
Bits 31:8 Type Read Only Default 000000h Reserved
HDA Defined Processing State: Writes to these bits set the Widget to the processing state as described below: '00'h; Processing Off. '01'h; Processing On. '02'h; Processing Benign. Benign state is not supported. Will be treated as "Processing Off". '03'h - `7F'h; - Reserved
Description
7:0
Read/Write
00h
6.15.4 Coefficient Index
The Coefficient Index is a zero-based index into the processing coefficient list which will be either read or written using the Processing Coefficient control. When the coefficient has been read or written to, the Coefficient Index will automatically increment by one so that the next Set Processing Coefficient verb will load the coefficient into the next slot. The auto-increment feature can be disabled by setting the Disable Coefficient Index Auto-Increment bit in the DAC Configuration Index Register (CIR=0003h). The auto-increment feature will "wrap around" at a Coefficient Index value of 1Fh, that is an index of 1Fh will be autoincremented to an index of 00h. If Coefficient Index is set to be greater than the number of "slots" in the processing coefficient list, unpredictable behavior will result if an attempt is made to Get or Set the processing coefficient. Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 11h Bits [19:16] Verb ID = Dh Bits [15:0] Parameter ID = 0000h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 11h Bits [19:16] Verb ID = 5h Bits [15:0] Parameter ID = xxxxh
Response Format:
Bits 31:16 15:0 Type Read Only Read/Write Default 0000h 0000h Reserved
Index n: Coefficient Index value.
Description
126
DS880F1
CS4207
6.15.5 Processing Coefficient
Processing Coefficient loads the value n into the widget's coefficient array at the index determined by the Coefficient Index control. When the coefficient has been read or written to, the Coefficient Index will automatically increment by one so that the next Set Processing Coefficient verb will load the coefficient into the next slot. Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 11h Bits [19:16] Verb ID = Ch Bits [15:0] Parameter ID = 0000h
Set Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 11h Bits [19:16] Verb ID = 4h Bits [15:0] Parameter ID = xxxxh
Response Format:
Bits 31:16 15:0 Type Read Only Read/Write Default 0000h 0000h Reserved
Value n: The value n of the 16 bit coefficient to set.
Description
6.15.6 Coefficient Registers
Processing Coefficient loads the 16-bit value n into the widget's coefficient array at the index determined by the Coefficient Index control. When the coefficient has been loaded, the Coefficient Index will automatically increment by one so that the next Set Processing Coefficient verb will load the coefficient into the next slot. Coefficient Index Register Summary:
Coefficient Index Register (CIR) 0000h 0001h 0002h 0003h 0004h 0005h-0007h Description S/PDIF RX/TX Interface Status S/PDIF RX/TX Interface Control ADC Configuration DAC Configuration Beep Configuration Reserved
DS880F1
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CS4207
6.15.6.1 S/PDIF RX/TX Interface Status (CIR = 0000h)
Bits 15:10 9 Type Read Only Read Only Default 0 0b Reserved
192 kHz Recovered Sample Rate - Measured audio sample rate of incoming S/PDIF data. A `1'b indicates a 192 kHz sample rate. 96 kHz Recovered Sample Rate - Measured audio sample rate of incoming S/PDIF data. A `1'b indicates a 96 kHz sample rate. 48 kHz Recovered Sample Rate - Measured audio sample rate of incoming S/PDIF data. A `1'b indicates a 48 kHz sample rate. 44.1 kHz Recovered Sample Rate - Measured audio sample rate of incoming S/PDIF data.A `1'b indicates a 44.1 kHz sample rate. 32 kHz Recovered Sample Rate - Measured audio sample rate of incoming S/PDIF data. A `1'b indicates a 32 kHz sample rate. CCRC - Channel Status Block Cyclic Redundancy Check bit. Updated on CS block boundaries, valid only in Pro mode.This bit will go
Description
8
Read Only
0b
7
Read Only
0b
6
Read Only
0b
5
Read Only
0b
4
Read Only
0b
high on occurrence of the error, and will stay high until the register is read. Reading the register resets this bit to 0, unless the error condition is still true.
0 - No error. 1 - Error.
BIP - Bi-phase error bit. Updated on sub-frame boundaries.This bit will go high on occur-
3
Read Only
0b
rence of the error, and will stay high until the register is read. Reading the register resets this bit to 0, unless the error condition is still true.
0 - No error. 1 - Bi-phase error. This indicates an error in the received bi-phase coding.
PAR - Parity bit. Updated on sub-frame boundaries. This bit will go high on occurrence of
2
Read Only
0b
the error, and will stay high until the register is read. Reading the register resets this bit to 0, unless the error condition is still true.
0 - No error.
1 - Parity error.
SPUL - S/PDIF Receiver Unlock Indicator 1 - The receiver is unlocked or has transition-ed from lock to unlock since the last read. 0 - The receiver is locked and has not transitioned from lock to unlock since the last read. SPL - S/PDIF Receiver Lock Indicator 1 - The receiver is locked or has transition-ed from unlock to lock since the last read. 0 - The receiver is unlocked and has not transition-ed from unlock to lock since the last read.
1
Read Only
0b
0
Read Only
0b
128
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CS4207
6.15.6.2 S/PDIF RX/TX Interface Control (CIR = 0001h)
Bits 15 14 Type Read Only Read/Write Default 0b 0b Reserved
TX 2 Enable: Routes S/PDIF Transmitter 2 to the GPIO1/DMIC_SDA2/SPDIF_OUT2 pin. 0 - The pin functions as GPIO1 or DMIC_SDA2, according to DMIC2 Enable. 1 - The pin functions as SPDIF_OUT2, regardless of DMIC2 Enable.
Description
13 12
Read/Write Read/Write
0b 0b
Reserved
TX 2 Raw Data Mode: Enables AES3 Direct Mode. In this mode, a direct copy of the received NRZ data from the HD Audio bus is sent to S/PDIF transmitter 2. 0 - Normal S/PDIF TX 2 Data Mode. 1 - Enable Raw S/PDIF TX 2 Data Mode. RX To TX 2 Loopthru: This bit is used to enable an internal loop through from the S/PDIF RX to S/PDIF TX 2. The path is a straight digital mux from input to output. No re-clocking is performed. 0 - Do not loop S/PDIF RX to S/PDIF TX 2. 1 - Enable S/PDIF RX to S/PDIF TX 2 loopthru. RX A/B Chnl Status Select: Specifies the channel from which to extract the channel status bits. `0'b - Select channel A status. `1'b - Select channel B status.
11
Read/Write
0b
10 9:8 7
Read/Write Read/Write Read/Write
0b 00b 0b
Reserved
TX 1 Raw Data Mode: Enables AES3 Direct Mode. In this mode, a direct copy of the received NRZ data from the HD Audio bus is sent to S/PDIF transmitter 1. 0 - Normal S/PDIF TX 1 Data Mode. 1 - Enable Raw S/PDIF TX 1 Data Mode. RX Raw Data Mode: Enables AES3 Direct Mode. In this mode, a direct copy of the received NRZ data from the S/PDIF receiver including the C, U, and V bits are transmitted to the HD Audio bus. The time slot occupied by the Z bit is used to indicate the location of the block start. 0 - Normal S/PDIF RX Data Mode. 1 - Enable Raw S/PDIF RX Data Mode. RX To TX 1 Loopthru: This bit is used to enable an internal loop through from the S/PDIF RX to S/PDIF TX 1. The path is a straight digital mux from input to output. No re-clocking is performed. 0 - Do not loop S/PDIF RX to S/PDIF TX 1. 1 - Enable S/PDIF RX to S/PDIF TX 1 loopthru.
6
Read/Write
0b
5
Read/Write
0b
DS880F1
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CS4207
HOLD[1:0] - Determines how received AES3 audio sample is affected when an receive error occurs. The errors that affect hold behavior are parity, bi-phase and confidence. HOLD has no effect in raw_spdif mode. 00 - hold last audio sample. 01 - replace the current audio sample with all zeros (mute). 10 - do not change the received audio sample. 11 - reserved TRUNC - Determines if the audio word length is set according to the incoming channel status data as decoded by the AUX[3:0] bits. The resulting word length in bits is 24 minus AUX[3:0]. The TRUNC function is valid only on PCM audio data. 0 - Incoming data is not truncated. 1 - Incoming data is truncated according to the length specified in the channel status data. TRUNC has no effect on output data if detected as being non-audio. SRC_MUTE - When SRC_MUTE is set to `1', the SRC will soft-mute when it loses lock and soft unmute when it regains lock. 0 - Soft mute disabled 1 - Soft mute enabled
4:3
Read/Write
01b
2
Read/Write
0b
1
Read/Write
0b
0
Read/Write
0b
Reserved
6.15.6.3 ADC Configuration (CIR = 0002h)
Bits 15 Type Read/Write Default 0b Description
URG (Unsolicited Response Gating): This bit allows unsolicited responses to be gated. 0 - Normal propagation of unsolicited responses. 1 - Unsolicited responses are gated if AFG is in D3. ADC2 Gain: This bit adjusts the gain of the Mic In 1/Line In 2 path for the given input topology. 0 - 6 dB gain added (pseudo-differential and single-ended mode). 1 - no gain added (fully differential mode). Note: This bit is OR'ed with the BTL bit in the
14
Read/Write
0b
Mic In 1/Line In 2 EAPD/BTL Enable Control.
13 Read/Write 0b
ADC1 Gain: This bit adjusts the gain of the Line In 1/Mic In 2 path for the given input topology. 0 - 6 dB gain added (pseudo-differential and single-ended mode). 1 - no gain added (not supported - test only).
130
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CS4207
12:11 Read/Write 00b
ADC2 Channel Mode[1:0]: Controls the channel mapping from the ADC2 output to the HDA bus. `00'b - ADC2 left channel is mapped to HDA left channel and ADC2 right channel is mapped HDA right channel (normal mode). `01'b - ADC2 left channel is mapped to both HDA left and right channels. ADC2 right channel is discarded (mono mode). `10'b - ADC2 right channel is mapped to both HDA left and right channels. ADC2 left channel is discarded (alternate mono mode). `11'b - ADC2 left channel is mapped to HDA right channel and ADC2 right channel is mapped to HDA left channel (channel swap mode). ADC1 Channel Mode[1:0]: Controls the channel mapping from the ADC1 output to the HDA bus. `00'b - ADC1 left channel is mapped to HDA left channel and ADC1 right channel is mapped HDA right channel (normal mode). `01'b - ADC1 left channel is mapped to both HDA left and right channels. ADC1 right channel is discarded (mono mode). `10'b - ADC1 right channel is mapped to both HDA left and right channels. ADC1 left channel is discarded (alternate mono mode). `11'b - ADC1 left channel is mapped to HDA right channel and ADC1 right channel is mapped to HDA left channel (channel swap mode).
10:9
Read/Write
00b
8:6 5
Read/Write Read/Write
000b 0b
Reserved
ADC2 PGA Mode: Sets the topology for the Mic In 1/Line In 2 PGA. 0 - Fully differential or pseudo-differential mode. 1 - Single-ended mode. ADC1 PGA Mode: Sets the topology for the Line In 1/Mic In 2 PGA. 0 - Pseudo-differential mode. 1 - Single-ended mode. ADC2 SZCMode[1:0]: Same function as ADC1. See below.
4
Read/Write
0b
3:2
Read/Write
10b
DS880F1
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CS4207
ADC1 SZCMode[1:0]: Sets the mode by which analog PGA and digital volume, and muting changes will be implemented.
`00'b - Immediate Change: When immediate change is selected, all level changes will take effect immediately in one step `01'b - Digital Immediate and Analog Zero Cross: Dictates that signal level changes, both muting and gain/attenuation, will occur immediately for digital volume changes between -13dB and 51dB and on a signal zero crossing for the Analog PGA volume changes from +12db to -12dB to minimize audible artifacts. The requested level change will occur after a timeout period (approx. ???? ms) if the signal does not encounter a zero crossing. Zero cross is independently monitored and implemented for each channel. `10'b - Digital Soft Ramp and Analog Soft Ramp: Allows level changes, both muting and gain/attenuation, to be implemented by incrementally ramping, if the level is between -13dB and -51dB at a rate of 1/8 dB per audio sample period using the digital volume control. For settings between +12dB and -12dB, level changes are to be implemented by incrementally ramping, at a rate of 1 dB per 8 audio sample periods using the analog PGA. If the analog PGA is being used for +10dB "boost" function or the Digital Mic is being used, then the digital soft ramp gain range will be from +12dB to -51dB and analog soft ramp will not be used. Soft ramp is independently monitored and implemented for each channel. `11'b - Digital Soft Ramp and Analog Zero Cross: Allows level changes, both muting and gain/attenuation, to be implemented by incrementally ramping, if the level is between -13dB and -51dB at a rate of 1/8 dB per audio sample period using the digital volume control. For settings between +12dB and -12dB, level changes are to be implemented on a signal zero crossing using the Analog PGA. The requested level change will occur after a timeout period (approx. ???? ms) if the signal does not encounter a zero crossing. If the analog PGA is being used for +10dB "boost" function or the Digital Mic is being used, then the digital soft ramp gain range will be from +12dB to -51dB and analog soft ramp will not be used. Soft ramp and zero cross are independently monitored and implemented for each channel.
1:0
Read/Write
10b
132
DS880F1
CS4207
6.15.6.4 DAC Configuration (CIR = 0003h)
Bits 15:13 Type Read/Write Default 000b Reserved
Enable DACs High Pass Filter: When set to `1'b, will enable a high pass filter to remove any DC component. `0'b - Disable HPF. `1'b - Enable HPF. Power Down Internal References (PDREF): When set to `1'b, will ramp the internal voltage references down. This should be used prior to removing operating voltages from the codec. `0'b - Normal Operation. `1'b - Power down internal references. Disable Coefficient Index Auto-Increment: Specifies if the Coefficient Index value will be automatically incremented following a read or write operation. Auto increment is supported by Vista OS. `0'b - auto increment coefficient index following a read or write. `1'b - do not auto increment coefficient index following a read or write.
Description
12
Read/Write
1b
11
Read/Write
0b
10
Read/Write
0b
9:7
Read/Write
000b
Reserved
Mute DAC Outputs on FIFO Error: Specifies to force a Mute condition if an under-run or over-run condition occurs on the HD Audio FIFO memory. The transition to Mute will occur as per the settings of each of the DACx SZCMode bit settings. `0'b - Disable Mute DAC Outputs on FIFO Error. `1'b - Enable Mute DAC Outputs on FIFO Error. DAC3 SZCMode[1:0]: Same function as DAC1. See below. DAC2 SZCMode[1:0]: Same function as DAC1. See below.
6
Read/Write
1b
5:4 3:2
Read/Write Read/Write
10b 10b
DS880F1
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CS4207
DAC1 SZCMode[1:0]: Sets the soft ramp and zero crossing detection modes by which volume and muting changes will be implemented.
`00'b - Immediate Change: When immediate change is selected, all level changes will take effect immediately in one step `01'b - Zero Cross: Dictates that signal level changes, both muting and gain/attenuation, will occur on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a timeout period (approximately???? ms) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel. `10'b - Soft Ramp: Allows level changes, both muting and gain/attenuation, to be implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1/8 dB per audio sample period. `11'b - Soft Ramp on Zero Cross: Dictates that signal level changes, both muting and gain/attenuation, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change will occur after a timeout period (approximately??? ms) if the signal does not encounter a zero crossing. The soft ramp on zero cross function is independently monitored and implemented for each channel.
1:0
Read/Write
10b
6.15.6.5 Beep Configuration (CIR = 0004h)
Bits 15:5 4 Type Read Only Read/Write Default 0 0b Reserved
DMIC2 Enable: Specifies whether GPIO1 or Digital Mic Interface 2 is enabled. `0'b - GPIO1 enabled, Digital Mic 2 disabled. `1'b - Digital Mic 2 enabled, GPIO1 disabled. DMIC1 Enable: Specifies whether GPIO0 or Digital Mic Interface 1 is enabled. `0'b - GPIO0 enabled, Digital Mic 1 disabled. `1'b - Digital Mic 1 enabled, GPIO0 disabled. DAC3 Beep Enable: This bit allows the output from the beep generator to be passed to DAC3. DAC2 Beep Enable: This bit allows the output from the beep generator to be passed to DAC2. DAC1 Beep Enable: This bit allows the output from the beep generator to be passed to DAC1.
Description
3
Read/Write
0b
2 1 0
Read/Write Read/Write Read/Write
1b 1b 1b
134
DS880F1
CS4207
6.16 Beep Generator Widget (Node ID = 13h)
6.16.1 Audio Widget Capabilities
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 13h Bits [19:8] Verb ID = F00h Bits [7:0] Parameter ID = 09h
Response Format:
Bits 31:24 23:20 19:16 15:12 11 10 9 8 7 6 5 4 3 2 1 0 Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only Default 00h 7h 0h 0h 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b Reserved
Type (TYP): Beep Generator Widget Delay (DLY): Number of sample delays through the widget.
Description
Reserved
L-R Swap (LRS): This widget is not capable of swapping the left and right channels. Power Control (PC): Power State control is not supported on this widget. Digital (DIG): Widget is not a digital widget. Connection List (CL): A connection list is not present on this widget. Unsolicited Capable (UC): Unsolicited Response is not supported on this widget. Processing Widget (PW): This widget does not contain "Processing Controls" parameters. Stripe (STRP): Stripping is not supported. Format Override (FO): This widget does not contain format information. Amplifier Parameter Override (APO): This widget does not contain amplifier parameters. Output Amplifier Present (OAP): Not present. Input Amplifier Present (IAP): Input amplifier is not present for this widget. Stereo (ST): Not supported.
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6.16.2 Beep Generation Control
Get Parameter Command Format:
Bits [31:28] CAd = X Bits [27:20] Node ID = 13h Bits [19:8] Verb ID = F0Ah Bits [7:0] Parameter ID = 00h
Set Parameter Command Format:
Bits [31:28] CAd = X Response Format: Bits 31:8 7:0 Type Read Only Read/Write Default 0000h 00h Reserved
Divider: When set to 0, beep generation is turned off. When set to any other value, beep generation is turned on and the frequency of the beep equals 12 kHz divided by this value.
Bits [27:20] Node ID = 13h
Bits [19:8] Verb ID = 70Ah
Bits [7:0] Parameter ID = xxh
Description
136
DS880F1
CS4207 7. APPLICATIONS
7.1 7.1.1 HD Audio Interface Multi-Channel Streams
The CS4207 codec supports multi-channel streams (streams with sample blocks containing more than two samples), on both inbound and outbound frames. Each of the 5 output converter widgets (DAC1/2/3, S/PDIF TX 1/2) can be associated with an individual stream, or multiple widgets can be grouped to share the same stream. A mix of shared and individual streams is also supported. Furthermore, the order in which channels are assigned to each widget is not constrained by design. However, the following limitations exist and must be avoided: * * a stream cannot contain channels that are not associated with any widget (unused channels), unless those channels appear last within the stream packet, after all other channels the same channel cannot be associated with more than one widget The same capabilities and limitations exist for the 3 input converter widgets (ADC1/2, S/PDIF RX). The following table gives some examples of valid and invalid stream formats:
Stream Format {A,B} {C,D} {E,F} {G,H} {I,J} {A, B, C, D, E, F, G, H, I, J} {A, B, C, D} {E, F} {A, B} {C, D} {A, B, C, D, E, F, G, H, I, J} {A, B, C, D} {A, B, C, D, E, F, G, H, I, J} {A, B, C, D, E, F, G, H, I, J} {A, B, C, D} DAC1 A, B A, B A, B G, H A, B A, B A, B DAC2 C, D C, D C, D E, F E, F C, D C, D DAC3 SPDO1 SPDO2 E, F E, F E, F C, D A, B G, H E, F G, H G, H I, J C, D I, J G, H A, B I, J I, J A, B C, D comment indiv. streams, in-order assignment shared stream, in-order assignment mixed shared and indiv. streams indiv. streams, out of order assignment shared stream, out of order assignment invalid: leading unused ch. (A, B) invalid: intermittent unused ch. (C, D) ok: trailing unused ch. (I, J) invalid: ch. assigned to mult. widgets
The curly brackets { } delineate each stream packet. The letters within curly brackets designate each channel within that stream packet. For instance the sequence "{A, B, C, D} {E, F}" denotes two streams one stream consisting of 4 channels A-D and one stream consisting of 2 channels E-F.
7.2 7.2.1
Analog Outputs Analog Supply Removal
In order to reduce audible artifacts, the analog reference is always powered up, even if the AFG has been transition-ed into D3 state. For maximum power savings during D3, it may be desirable to completely remove the analog supplies on the system level. Doing so would cause an uncontrolled discharge of the internal reference and hence audible artifacts, and must therefore be preceded with a controlled reference ramp-down, which is initiated by setting the PDREF bit in the DAC Configuration (CIR = 0003h) register of the Vendor Processing Widget (Node ID = 11h).
7.3
Digital Mic Inputs
For each ADC, the data from the digital mic input pin widgets are multiplexed with the data from the analog line/mic input pin widgets, and only one pin widget can be selected at any given time. Furthermore, the data pins for the DMIC interface (DMIC_SDA1/2) are multiplexed with the GPIO0/1 pins and default to GPIO. In order to successfully setup the data path for a digital microphone, the following steps have to be followed:
DS880F1
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CS4207
* * * * * clear the TX 2 Enable bit in the S/PDIF RX/TX Interface Control (CIR = 0001h) register of the Vendor Processing Widget (Node ID = 11h) (only required for DMIC2) set the DMIC1 Enable and/or DMIC2 Enable bit in the Beep Configuration (CIR = 0004h) register of the Vendor Processing Widget (Node ID = 11h) set the INE bit in the Pin Widget Control of the Digital Mic In 1 Pin Widget (Node ID = 0Eh) and/or the Digital Mic In 2 Pin Widget (Node ID = 12h) for DMIC1 set the Connection Index in the ADC2 Connection Select Control of the ADC2 Input Converter Widget (Node ID = 06h) to a value of 01h for DMIC2 set the Connection Index in the ADC1 Connection Select Control of the ADC1 Input Converter Widget (Node ID = 05h) to a value of 01h
The clock signal for the DMIC interface (DMIC_SCL) will be enabled if at least one of the DMIC data paths has been configured as described above.
138
DS880F1
CS4207 8. ANALOG OUTPUT AND FILTERING
The Cirrus Application Note titled Design Notes for a 2-Pole Filter with Differential Input, available as AN48 at www.cirrus.com, discusses the second-order Butterworth filter and differential-to-single-ended converter that was implemented on the CS4207 evaluation board. Figure 9 illustrates this implementation. If only single-ended outputs from the CS4207 are required, the passive output filter shown in Figure 10 can be used.
3300 pF 2.26 k 1000 pF 1.5 k + 2200 pF C0G 1.05 k 220 pF C0G 220
CS4207
C0G
LINEOUTx LINEOUTx +
22 F
4.53 k
Analog Output
22 F
2.05 k 6800 pF
698
AGND
C0G
Figure 9. Differential to Single-Ended Output Filter
CS4207 LINEOUTx +
4.7 F +
562
2700 pF 47.5 k
Analog Output
AGND
Figure 10. Passive Single-Ended Output Filter
9. PCB LAYOUT CONSIDERATIONS
9.1 Power Supply, Grounding
As with any high-resolution converter, the CS4207 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 1 on page 11 and Figure 2 on page 12 show the recommended power arrangements, with VA connected to a clean supply. VD, which powers the digital circuitry, may be run from the system logic supply. To achieve full analog performance, it is strongly recommended that the following rules be followed: * * place the cap between VBIAS and VA_REF as close to the codec as possible to minimize trace impedance keep the traces for VA and VA_REF separate as much as possible and only connect them at the supply
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Decoupling capacitors should be as close to the pins of the CS4207 as possible. The low value ceramic capacitor should be closest to the pin and should be mounted on the same side of the board as the CS4207 to minimize inductance effects. All signals, especially clocks, should be
DS880F1
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CS4207
kept away from the FILT+ and VCOM pins in order to avoid unwanted coupling into the modulators. The CDB4207 evaluation board demonstrates the optimum layout and power supply arrangements.
9.2
QFN Thermal Pad
The CS4207 is available in a compact QFN package. The underside of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers. In split ground systems, it is recommended that this thermal pad be connected to AGND for best performance. The CS4207 evaluation board demonstrates the optimum thermal pad and via configuration.
10.PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at 1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channel pairs. Measured for each channel at the converter's output with no signal to the input under test and a full-scale signal applied to the other channel. Units in decibels.
Interchannel Gain Mismatch
The gain difference between left and right channel pairs. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog output for a full-scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
140
DS880F1
CS4207 11.PACKAGE DIMENSIONS 48LD QFN (6 X 6 mm BODY) PACKAGE DRAWING
D
D2
L
E
e
E2
1
b
TOP VIEW
A A1 A3
BTM VIEW
SEATING PLANE
SIDE VIEW
Notes: 1) Controlling dimensions are in mm. 2) Dimensioning and tolerancing conform to ASME Y14.5m-1994 3) Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 4) Reference JEDEC MO-229
DIM
A A1 A3 b D D2 E E2 e L
MIN
0.70 0.00 0.15 4.25 4.25 0.35
NOM
0.75 0.20 BSC 0.20 6.00 BSC 4.40 6.00 BSC 4.40 0.40 BSC 0.45
MAX
0.80 0.05 0.25 4.50 4.50 0.55
THERMAL CHARACTERISTICS
Parameter Junction to Ambient Thermal Impedance
2 Layer Board 4 Layer Board
Symbol JA
Min -
Typ tbd tbd
Max -
Units C/Watt
DS880F1
141
CS4207 12.ORDERING INFORMATION
Product
CS4207
Description
Package Pb-Free
Yes
Grade
Temp Range
Container
Rail
Order #
CS4207-CNZ/C1
CS4207 CDB4207
Low Power, 4-In/6-Out HD Audio CODEC with 48L-QFN Headphone Amp Low Power, 4-In/6-Out HD Audio CODEC with 48L-QFN Headphone Amp CS4207 Evaluation Board
Commercial -40C to +85C
Tape & Reel CS4207-CNZR/C1 Rail CS4207-DNZ CS4207-DNZR CDB4207
Yes -
Automotive -40C to +105C -
Tape & Reel -
13.REFERENCES
1. Intel Corporation, High Definition Audio Specification, Revision 1.0, April 15, 2004. http://download.intel.com/standards/hdaudio/pdf/HDAudio_03.pdf
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CS4207 14.REVISION HISTORY
Revision
A1 B4 Initial Release First Customer Release
Changes
* Updated "Typical Connection Diagrams" on page 11 to reflect addition of VA_REF pin * Updated "Characteristic and Specifications" on page 13 * Changed MISC[0] default to `0' in "Configuration Default" on page 95, "Digital Mic In 1 Configuration Default" on page 109, "Digital Mic In 2 Configuration Default" on page 110, "S/PDIF Transmitter 1 Configuration Default" on page 123, and "S/PDIF Transmitter 2 Configuration Default" on page 124.
PP1
* Corrected IEN bit description in "Pin Widget Control" on page 109 * Clarified URG bit description in "ADC Configuration (CIR = 0002h)" on page 130 * Added "HD Audio Interface" on page 137 * Added "Digital Mic Inputs" on page 137 * Updated "Analog Output and Filtering" on page 139 * Updated "Characteristic and Specifications" on page 13 (DAC1/HPOUT)
PP3
* Consistent terminology of Line Out 1 and Line Out 2 throughout the document
F1
* Production Release
DS880F1
143
CS4207
Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. AC-3 is a registered trademark of Dolby Laboratories, Inc.
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